Timing Basics in Static Timing Analysis (STA): Delay Models, Sequential Timing, and Wire Delays

Timing Basics in Static Timing Analysis (STA)

Static Timing Analysis (STA) is one of the most important verification techniques used in modern VLSI design. Before a chip is manufactured, engineers must verify that every signal reaches its destination within the required clock period. Even if a design passes functional simulation, it may still fail after fabrication because of timing violations.

Unlike simulation, Static Timing Analysis mathematically analyzes every timing path without applying input test vectors. This makes STA significantly faster and capable of analyzing millions of timing paths efficiently.

What is Static Timing Analysis?
Why STA is Required
Propagation Delay
Contamination Delay
Cell Delay Models
Combinational Gate Delay
Sequential Timing
Setup Time
Hold Time
Wire Delay
RC Delay Model
PVT Corners
Worked Examples
Interview Questions
Key Takeaways

What is Static Timing Analysis?

Static Timing Analysis (STA) is a vector-less timing verification technique used to determine whether every timing path in a digital circuit satisfies setup and hold timing requirements. Rather than simulating the functionality of the design, STA computes delays mathematically using standard-cell timing libraries and timing constraints.

STA is performed throughout the ASIC implementation flow—from synthesis to physical design and signoff—to ensure that the chip can operate correctly at the target clock frequency.

Where is STA Performed?

After RTL Synthesis
During Place and Route (PnR)
After Clock Tree Synthesis (CTS)
Before Tape-out
During Timing Signoff

Typical ASIC Design Flow

Stage	Description
RTL Design	Design functionality is described using Verilog/SystemVerilog.
Synthesis	RTL is converted into a gate-level netlist.
Static Timing Analysis	Timing is verified using timing libraries and constraints.
Physical Design	Placement, CTS and routing are performed.
Signoff	Final timing verification before tape-out.

Key Point

Static Timing Analysis verifies timing without running simulations. Its primary objective is to ensure that every timing path has positive timing slack.

Why is Static Timing Analysis Required?

As modern SoCs contain millions of gates, simulating every possible input combination becomes impractical. Static Timing Analysis provides a mathematical solution that analyzes every timing path quickly and accurately.

Advantages of STA

Very fast timing verification
No simulation vectors required
Detects setup timing violations
Detects hold timing violations
Supports very large ASIC and SoC designs
Analyzes multiple PVT corners
Reduces silicon re-spins
Helps achieve timing closure before tape-out

Inputs Required by STA Tools

Input	Purpose
Gate-Level Netlist	Represents the synthesized design.
Liberty (.lib)	Contains timing information for standard cells.
SDC File	Defines clocks and timing constraints.
SPEF File	Contains extracted wire parasitics.

Important

Without accurate timing constraints and timing libraries, the STA report will not accurately represent real silicon performance.

Understanding Delay in Digital Circuits

Whenever an input signal changes, the output does not respond immediately. Every logic gate and interconnect introduces a finite amount of delay. Static Timing Analysis evaluates these delays to determine whether signals arrive within the required clock period.

Two important delay parameters used throughout STA are Propagation Delay and Contamination Delay. These parameters are essential for setup and hold timing analysis.

Delay Type	Symbol	Meaning	Used For
Propagation Delay	t_pd	Maximum delay from input to output	Setup Analysis
Contamination Delay	t_cd	Minimum delay from input to output	Hold Analysis

Key Concept

Propagation delay represents the worst-case delay, whereas contamination delay represents the best-case delay.

Propagation Delay

Propagation delay is the maximum time required for a change at the input of a logic gate to appear at its output. Since it represents the longest possible delay through a gate, STA uses propagation delay while checking setup timing.

Formula

t_pd = Output Transition Time − Input Transition Time

Example

Parameter	Value
Input Transition	5.0 ns
Output Transition	5.8 ns

Calculation

t_pd = 5.8 − 5.0 = 0.8 ns

Remember

Propagation delay is always used for Setup Timing Analysis.

Contamination Delay

Contamination delay is the minimum time required before the output of a logic gate begins changing after an input transition. It represents the earliest possible output transition and is therefore used in hold timing analysis.

Formula

t_cd = First Output Transition − Input Transition

Example

Parameter	Value
Input Transition	10.0 ns
Output Starts Changing	10.15 ns

t_cd = 10.15 − 10.0

Contamination Delay = 0.15 ns

Important

Very small contamination delay can cause Hold Time Violations because new data reaches the receiving flip-flop too early.

Propagation Delay vs Contamination Delay

Parameter	Propagation Delay	Contamination Delay
Definition	Maximum Delay	Minimum Delay
Used In	Setup Timing	Hold Timing
Represents	Worst Case	Best Case
Usually Larger?	Yes	No
Symbol	t_pd	t_cd

Cell Delay Models

The delay introduced by a logic gate is not fixed. It depends on several electrical and physical characteristics. Timing libraries characterize every standard cell under different operating conditions, allowing STA tools to estimate delays accurately.

Factors Affecting Cell Delay

Input Transition (Slew)
Output Load Capacitance
Drive Strength
Supply Voltage
Temperature
Manufacturing Process Variation

Factor	Impact on Delay
Higher Load Capacitance	Delay Increases
Higher Fanout	Delay Increases
Higher Drive Strength	Delay Decreases
Lower Supply Voltage	Delay Increases
Higher Temperature	Delay Increases

General Delay Equation

Cell Delay = f (Input Slew, Output Load, Voltage, Temperature, Process)

Example

Parameter	Value
Input Slew	60 ps
Output Load	25 fF
Cell	NAND X2
Temperature	25°C

The STA tool uses these parameters to search the corresponding lookup table in the .lib file and calculates the actual delay automatically.

Did You Know?

All timing information used by STA tools such as Synopsys PrimeTime and Cadence Tempus is stored inside the Liberty (.lib) timing library.

Combinational Gate Delay

A combinational circuit produces outputs based solely on the current values of its inputs. Every logic gate introduces a finite delay before its output changes. During Static Timing Analysis, the delay through a combinational path is calculated by adding the delays of all gates and the connecting interconnects.

Factors Affecting Gate Delay
✔ Gate Type (INV, NAND, NOR, XOR)
✔ Input Slew
✔ Output Load Capacitance
✔ Fanout
✔ Supply Voltage
✔ Temperature
✔ Process Corner

Gate Delay Formula

Gate Delay = f (Load, Slew, Process, Voltage, Temperature)

Example

Component	Delay
Inverter	0.12 ns
NAND Gate	0.18 ns
Wire Delay	0.10 ns

Total Delay

0.12 + 0.18 + 0.10 = 0.40 ns

💡 Design Tip

Reducing fanout, improving cell drive strength, and shortening routing paths help reduce combinational delay.

Sequential Timing

Unlike combinational circuits, sequential circuits store data using memory elements such as flip-flops and latches. Their operation depends on both the input data and the clock signal.

Three important timing parameters are used in STA:

Clock-to-Q Delay (t_cq)
Setup Time (t_setup)
Hold Time (t_hold)

Clock-to-Q Delay

Clock-to-Q delay is the time required for the output (Q) of a flip-flop to change after the active edge of the clock.

t_cq = Q Transition Time − Clock Edge Time

Example

Clock Edge	Q Changes	Clock-to-Q Delay
12.00 ns	12.08 ns	0.08 ns

Remember

Clock-to-Q delay contributes to both setup and hold timing calculations.

Setup Time

Setup time is the minimum duration for which the input data must remain stable before the active clock edge. If data changes too close to the clock edge, the flip-flop may capture incorrect data.

Setup Timing Condition

Arrival Time ≤ Required Time

Required Time Formula

Required Time = Clock Period − Setup Time − Clock Uncertainty

Setup Slack Formula

Setup Slack = Required Time − Arrival Time

Worked Example

Parameter	Value
Clock Period	2 ns
Setup Time	0.15 ns
Clock Uncertainty	0.05 ns
Arrival Time	1.55 ns

Required Time

2.00 − 0.15 − 0.05 = 1.80 ns

Setup Slack

1.80 − 1.55 = +0.25 ns

✔ Positive Setup Slack = PASS

Hold Time

Hold time is the minimum duration for which data must remain stable after the active clock edge. If data changes too quickly, a hold violation occurs.

Hold Slack Formula

Hold Slack = Arrival Time − Required Hold Time

Worked Example

Parameter	Value
Clock-to-Q Delay	0.08 ns
Logic Delay	0.10 ns
Required Hold Time	0.14 ns

Arrival Time = 0.08 + 0.10 = 0.18 ns

Hold Slack = 0.18 − 0.14 = +0.04 ns

✔ Positive Hold Slack = PASS

Setup Time vs Hold Time

Feature	Setup Time	Hold Time
Checks	Late Data	Early Data
Violation Cause	Slow Path	Fast Path
Slack Formula	Required − Arrival	Arrival − Required
Common Fix	Reduce Delay / Lower Clock Frequency	Add Delay Buffers

🎯 Interview Tip

Setup checks the maximum delay, while Hold checks the minimum delay. Every timing path must satisfy both constraints before tape-out.

Wire (Interconnect) Delay

As technology scales to advanced nodes such as 7 nm, 5 nm, and 3 nm, interconnect delay often becomes larger than gate delay. Every metal wire possesses resistance (R) and capacitance (C), which slow down signal propagation.

Factors Affecting Wire Delay

Parameter	Effect
Longer Wire	Higher Delay
Higher Resistance	Higher Delay
Higher Capacitance	Higher Delay
Lower Metal Layer	Higher Resistance
Routing Congestion	Higher Delay

💡 Tip

During Physical Design, reducing routing length significantly improves timing performance.

RC Delay Model

Interconnects are modeled using resistance and capacitance networks. One of the simplest and most widely used approximations is the Elmore Delay Model.

Formula

Delay ≈ Σ (Resistance × Downstream Capacitance)

Example

Segment	Resistance	Capacitance
R₁	20 Ω	2 pF
R₂	15 Ω	1 pF

Approximate Delay

(20 × 3) + (15 × 1)

≈ 75 ps

Process, Voltage and Temperature (PVT)

Process variation, supply voltage and operating temperature directly affect transistor switching speed. Therefore, STA is performed across multiple operating corners.

Corner	Process	Voltage	Temperature	Delay
SS	Slow	Low	High	Maximum
TT	Typical	Typical	Typical	Nominal
FF	Fast	High	Low	Minimum

Why Multiple Corners?

A design that works only at the Typical corner may fail after manufacturing. PVT analysis guarantees reliable silicon under real-world operating conditions.

Complete Timing Path Example

Component	Delay
Inverter	0.12 ns
Wire	0.10 ns
NAND Gate	0.18 ns
Clock-to-Q	0.08 ns

Total Delay

0.12 + 0.10 + 0.18 + 0.08 = 0.48 ns

Summary

Parameter	Symbol	Purpose
Propagation Delay	t_pd	Maximum Delay
Contamination Delay	t_cd	Minimum Delay
Clock-to-Q	t_cq	Flip-Flop Output Delay
Setup Time	t_setup	Data Stable Before Clock
Hold Time	t_hold	Data Stable After Clock
Wire Delay	RC Delay	Interconnect Delay

Frequently Asked Interview Questions

What is Static Timing Analysis?
What is the difference between Setup and Hold Time?
Why is Propagation Delay used for Setup Analysis?
Why is Contamination Delay used for Hold Analysis?
What is Clock-to-Q Delay?
Explain Timing Slack.
What is Elmore Delay?
Why is PVT Analysis important?
What is contained inside a Liberty (.lib) file?
How do you fix Setup and Hold Violations?

Key Takeaways

Static Timing Analysis verifies timing without simulation.
Propagation Delay is used for Setup Analysis.
Contamination Delay is used for Hold Analysis.
Setup checks maximum delay while Hold checks minimum delay.
Wire delay dominates in advanced technology nodes.
RC and Elmore models estimate interconnect delay.
PVT analysis ensures reliable silicon.
Positive Slack indicates successful timing closure.

Conclusion

Static Timing Analysis is one of the most important stages in the ASIC design flow. By understanding propagation delay, contamination delay, setup time, hold time, RC delay models, and PVT analysis, engineers can detect timing violations before fabrication and achieve successful timing closure.

📘 The Silicon Stack

Helping students and professionals master ASIC Design, RTL Design, Physical Design, Static Timing Analysis, UVM, and Verification through practical learning resources.

ASIC Design Flow Explained
Setup and Hold Time Explained
Clock Tree Synthesis (CTS)
Introduction to Physical Design
SDC Constraints Explained
CMOS Inverter Working
Flip-Flops in Digital Design
Static Timing Analysis Interview Questions

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