Skip to main content

Interrupt Controller in SoC: A Complete Beginner's Guide to Working, Types, Priority Handling & Architecture

Image
By

 

Interrupt Controller in SoC: A Complete Beginner's Guide to Working, Types, Priority Handling & Architecture

Modern processors interact with hundreds of hardware peripherals, including timers, keyboards, USB controllers, UARTs, Ethernet interfaces, DMA controllers, sensors, and storage devices. These peripherals continuously generate events that require the processor's attention.

If the CPU constantly checked every peripheral to determine whether it needed servicing, most of its processing power would be wasted. Instead, modern computer systems use an Interrupt Controller, which efficiently collects, prioritises, and forwards interrupt requests to the processor only when necessary.

The Interrupt Controller is one of the most important hardware blocks in System-on-Chip (SoC) design, Computer Architecture, Embedded Systems, Operating Systems, ASIC Design, and ASIC Verification.

In this article, you'll learn what an Interrupt Controller is, why it is required, how it works, its architecture, types, registers, priority handling, interrupt flow, applications, and verification concepts.

What is an Interrupt?

An Interrupt is a signal generated by hardware or software that temporarily stops the normal execution of the CPU and requests immediate attention.

When an interrupt occurs:

  1. CPU pauses the current program.

  2. Saves its current execution context.

  3. Executes a special function called the Interrupt Service Routine (ISR).

  4. Restores the saved context.

  5. Resumes execution of the interrupted program.

Instead of continuously checking every peripheral (polling), the CPU responds only when an event actually occurs.

What is an Interrupt Controller?

An Interrupt Controller is a dedicated hardware block that manages interrupt requests from multiple peripherals and forwards the appropriate interrupt to the CPU.

Its responsibilities include:

  • Collecting interrupt requests

  • Prioritising multiple interrupt sources

  • Masking or enabling interrupts

  • Sending interrupt requests to the CPU

  • Tracking active interrupts

  • Supporting nested interrupts

  • Clearing interrupts after servicing

Without an interrupt controller, every peripheral would need a direct connection to the processor, making the system complex and difficult to scale.

Why Do We Need an Interrupt Controller?

Imagine a processor connected to:

  • Timer

  • UART

  • USB

  • DMA

  • GPIO

  • Ethernet

  • SPI

  • I²C

Each device can generate interrupts independently.

Without an Interrupt Controller:

  • CPU would need numerous interrupt input pins.

  • Simultaneous interrupts would create conflicts.

  • No mechanism would exist to determine which interrupt should be serviced first.

  • CPU performance would decrease significantly.

The Interrupt Controller solves these problems by acting as a central interrupt management unit.

Polling vs Interrupts

Before understanding the controller, it helps to compare polling and interrupts.



Position of the Interrupt Controller in an SoC

A simplified architecture looks like this:

How Does an Interrupt Controller Work?

The overall sequence is straightforward:

  1. A peripheral generates an interrupt request.

  2. The Interrupt Controller captures the request.

  3. The controller determines its priority.

  4. The highest-priority interrupt is forwarded to the CPU.

  5. CPU acknowledges the interrupt.

  6. CPU saves its execution context.

  7. CPU executes the Interrupt Service Routine (ISR).

  8. ISR clears the interrupt source.

  9. CPU sends an End Of Interrupt (EOI) signal.

  10. Controller removes the interrupt from its pending list.

  11. CPU resumes normal execution.

This process typically completes within a few microseconds or less in modern processors.

Internal Architecture of an Interrupt Controller

A typical interrupt controller consists of several internal hardware blocks.

1. Interrupt Input Logic

This block receives interrupt requests from peripherals.

Examples:

  • Timer IRQ

  • UART IRQ

  • DMA IRQ

  • GPIO IRQ

  • Ethernet IRQ

It synchronises and validates incoming interrupt signals.

2. Interrupt Request Register (IRR)

The IRR stores all pending interrupt requests.


.

3. Priority Resolver

If multiple interrupts occur simultaneously, the Priority Resolver determines which interrupt should be serviced first.

Priority may be:

  • Fixed

  • Programmable

  • Rotating

  • Dynamic

The selected interrupt is forwarded to the CPU.

4. Interrupt Mask Register (IMR)

The IMR allows software to enable or disable interrupts.

Example:

1 = Interrupt Enabled
0 = Interrupt Masked

Masking is useful when:

  • Debugging

  • Performing critical operations

  • Preventing unnecessary interrupts

5. In-Service Register (ISR)

This register keeps track of interrupts currently being serviced.

It prevents:

  • Duplicate servicing

  • Incorrect nesting

  • Conflicts between interrupts

6. End of Interrupt (EOI) Logic

After the Interrupt Service Routine finishes:

  • CPU sends an EOI signal.

  • Controller clears the interrupt.

  • Next pending interrupt becomes eligible for service.

Types of Interrupts

Interrupts can be classified in several ways.

1. Hardware Interrupts

Generated by hardware devices.

Examples:

  • Keyboard

  • Timer

  • UART

  • DMA

  • Ethernet

  • GPIO

2. Software Interrupts

Generated by software instructions.

Used for:

  • System calls

  • Operating system services

  • Debugging

3. Maskable Interrupts

These interrupts can be enabled or disabled by software.

Examples:

  • UART receive interrupt

  • Timer interrupt

4. Non-Maskable Interrupt (NMI)

Cannot be disabled.

Used for critical situations such as:

  • Watchdog timeout

  • Power failure

  • Hardware fault

  • Memory parity error

Priority Handling

Modern processors receive interrupts from many sources.

Fixed Priority

Priority order never changes.



Programmable Priority

Software assigns priorities dynamically.

Advantages:

  • Flexible

  • Suitable for operating systems

  • Better resource allocation

Rotating Priority

After servicing one interrupt:

That interrupt moves to the lowest priority.

This prevents starvation of lower-priority devices.

Interrupt Trigger Types

Interrupts can be triggered in two ways.

Interrupt Service Routine (ISR)

An Interrupt Service Routine is the function executed when an interrupt occurs.

Typical ISR steps:

  1. Save CPU context.

  2. Identify interrupt source.

  3. Service the peripheral.

  4. Clear interrupt flag.

  5. Send End Of Interrupt (EOI).

  6. Restore CPU context.

  7. Return to the interrupted program.

ISRs should be:

  • Short

  • Efficient

  • Deterministic

Long ISRs increase interrupt latency and reduce system performance.

Nested Interrupts

Sometimes a higher-priority interrupt arrives while another ISR is executing.

Example:

CPU is servicing:

UART interrupt

During execution:

Watchdog interrupt occurs.

Since Watchdog has higher priority:

  1. UART ISR is paused.

  2. Watchdog ISR executes.

  3. CPU returns to UART ISR.

  4. Original program resumes.

This is called Nested Interrupt Handling.

Daisy-Chained vs Centralised Interrupt Controllers

Daisy-Chained

Interrupts pass from one peripheral to another.

Advantages:

  • Simple

  • Low cost

Disadvantages:

  • Longer latency

  • Limited scalability

Centralised Controller

All peripherals connect directly to one controller.

Advantages:

  • Faster

  • Better priority handling

  • Easier expansion

  • Used in modern SoCs

Interrupt Latency

Interrupt latency is the time between:

Interrupt generation

and

Execution of the first ISR instruction.

Latency depends on:

  • CPU pipeline

  • Cache state

  • Controller design

  • Context save time

  • Operating system

Reducing latency is essential in real-time systems.

Real-World Example

Imagine a smartphone:

While watching a video:

  • Timer generates scheduling interrupt.

  • Touchscreen generates touch interrupt.

  • Wi-Fi receives packets.

  • Audio codec requests new samples.

  • Battery controller reports low battery.

The Interrupt Controller:

  • Collects all requests.

  • Prioritises them.

  • Delivers one interrupt at a time.

  • Ensures critical events are serviced first.

Without it, the CPU would struggle to manage these simultaneous events efficiently.

Popular Interrupt Controllers

Several interrupt controllers are widely used in industry.

ARM Generic Interrupt Controller (GIC)

Used in ARM Cortex-A processors.

Features:

  • Hundreds of interrupt sources

  • Multi-core support

  • Nested interrupts

  • Programmable priorities

Nested Vectored Interrupt Controller (NVIC)

Used in ARM Cortex-M microcontrollers.

Features:

  • Fast interrupt response

  • Vector table

  • Hardware prioritisation

  • Low latency

Advanced Programmable Interrupt Controller (APIC)

Used in x86 processors.

Features:

  • Multi-core interrupt management

  • Inter-processor interrupts (IPI)

  • High scalability

Verification of Interrupt Controllers

Interrupt Controllers are thoroughly verified before tape-out.

Typical verification scenarios include:

  • Single interrupt

  • Multiple simultaneous interrupts

  • Priority resolution

  • Interrupt masking

  • Nested interrupts

  • End Of Interrupt handling

  • Interrupt acknowledgement

  • Spurious interrupts

  • Level-triggered interrupts

  • Edge-triggered interrupts

  • Reset behaviour

Verification environments typically use SystemVerilog, UVM, assertions, and functional coverage.

Advantages of an Interrupt Controller

  • Efficient CPU utilisation

  • Faster event handling

  • Reduced polling overhead

  • Supports multiple peripherals

  • Prioritised interrupt servicing

  • Lower power consumption

  • Improved real-time performance

  • Scalable architecture

  • Simplified CPU design

Disadvantages

  • Additional hardware complexity

  • Increased silicon area

  • Verification challenges

  • Priority configuration complexity

  • Interrupt latency if many requests are pending

Applications

Interrupt Controllers are found in almost every digital system, including:

  • Smartphones

  • Laptops

  • Servers

  • Automotive ECUs

  • Industrial controllers

  • Networking equipment

  • IoT devices

  • Medical electronics

  • Aerospace systems

  • Consumer electronics

  • FPGA-based systems

  • ASICs and SoCs

Best Practices

When designing or verifying an Interrupt Controller:

  • Define clear interrupt priorities.

  • Keep ISRs as short as possible.

  • Mask unnecessary interrupts during critical operations.

  • Avoid interrupt starvation by using programmable or rotating priorities when appropriate.

  • Verify all interrupt combinations and edge cases.

  • Measure interrupt latency in timing-critical systems.

  • Ensure proper handling of nested interrupts and EOI.

Future Trends

Modern interrupt systems continue to evolve with advances in processor design.

Emerging trends include:

  • AI-assisted interrupt scheduling

  • Virtualised interrupt controllers

  • Chiplet-aware interrupt routing

  • Hardware-assisted real-time prioritisation

  • Multi-core interrupt balancing

  • Low-power interrupt management for IoT devices

These innovations help maintain responsiveness while supporting increasingly complex SoCs.

Conclusion

The Interrupt Controller is a critical component of every modern SoC. It efficiently manages interrupt requests from multiple peripherals, prioritises competing events, and ensures that the CPU responds quickly to the most important tasks.

By eliminating the need for constant polling, the Interrupt Controller improves CPU efficiency, reduces power consumption, and enables scalable, real-time system operation. Features such as programmable priorities, interrupt masking, nested interrupt support, and End Of Interrupt handling make it indispensable in embedded systems, processors, and advanced SoCs.

Whether you're learning Computer Architecture, Embedded Systems, VLSI, ASIC Design, or ASIC Verification, understanding the Interrupt Controller provides a strong foundation for exploring operating systems, processor design, and hardware–software interaction.

Frequently Asked Questions (FAQs)

1. What is an Interrupt Controller?

An Interrupt Controller is a hardware module that receives interrupt requests from multiple devices, prioritises them, and forwards the appropriate interrupt to the CPU.

2. Why is an Interrupt Controller needed?

It allows the CPU to respond efficiently to hardware and software events without continuously polling peripherals, improving system performance and reducing power consumption.

3. What is the difference between a maskable and a non-maskable interrupt?

Maskable interrupts can be enabled or disabled by software, whereas non-maskable interrupts (NMIs) cannot be disabled and are reserved for critical system events.

4. What is an Interrupt Service Routine (ISR)?

An ISR is a special software routine executed by the CPU to handle a specific interrupt, after which normal program execution resumes.

5. Which interrupt controllers are commonly used today?

Popular implementations include the ARM Generic Interrupt Controller (GIC), Nested Vectored Interrupt Controller (NVIC), and Advanced Programmable Interrupt Controller (APIC), depending on the processor architecture.



Labels:

Comments

Post a Comment

Popular posts from this blog

Module 1 — SystemVerilog Basics

By
VLSI Verification  •  SystemVerilog Series Module 1 — SystemVerilog Basics A complete, example-driven walkthrough of SystemVerilog fundamentals: data types, variables vs nets, arrays of every flavor, strings, enums, structs, unions, and typedef — the building blocks every verification engineer needs before UVM. 🧩 Beginner → Intermediate ⏱ ~25 min read 💻 Code Examples Included 📑 Table of Contents Introduction to SystemVerilog Verilog vs SystemVerilog Data Types: 2-State vs 4-State Logic Variables and Nets Arrays: Packed vs Unpacked Dynamic Arrays Queues Associative Arrays Strings Enumerations Structures Unions Typedef 1 Introduction to SystemVerilog SystemVerilog (IEEE 1800) is a unified hardware description and verification language (HDVL). It extends Verilog (IEEE 1364) with powerful constructs for design (interfaces, always_comb/always_ff, enhanced d...
Post a Comment
Read more

GPU Memory System & Interconnect: How Data Travels Inside a Modern GPU

By
GPU Memory System & Interconnect: How Data Travels Inside a Modern GPU Modern GPUs deliver incredible computing power by processing thousands of operations simultaneously. While compute cores often receive the spotlight, the real performance of a GPU depends heavily on how efficiently data moves between memory and compute units. A GPU memory system is designed to provide extremely high bandwidth while keeping latency as low as possible. This is achieved through a collection of specialized hardware components working together, including the Memory Controller, HBM/GDDR memory, Crossbar, Network-on-Chip (NoC), DMA Engine, PCIe Interface, and NVLink. In this article, we'll explore each component in detail and understand how they collectively enable high-performance parallel computing. Why Does GPU Memory Matter? Every GPU application—from gaming and graphics rendering to AI model training and scientific simulations—requires continuous movement of enormous amounts of data. For examp...
Post a Comment
Read more

Clock Domain Crossing (CDC): A Complete Beginner's Guide to Metastability, Synchronizers & Safe Data Transfer

By
Clock Domain Crossing (CDC): A Complete Beginner's Guide to Metastability, Synchronizers & Safe Data Transfer Modern System-on-Chip (SoC) designs rarely operate with a single clock. Instead, different modules such as CPUs, GPUs, memory controllers, communication interfaces, and peripherals often run at different clock frequencies or even use completely independent clock sources . When data moves from one clock domain to another, timing uncertainty can cause serious problems such as metastability , data corruption , and unpredictable system behaviour . This challenge is known as Clock Domain Crossing (CDC) . CDC is one of the most important topics in ASIC Design , RTL Design , ASIC Verification , FPGA Design , and SoC Architecture . Every modern chip—from smartphones to automotive processors—uses CDC techniques to ensure reliable communication between multiple clock domains. In this article, we'll explore CDC fundamentals, metastability, synchronization techniques, asynchro...
Post a Comment
Read more

AXI Verification Interview Questions and Real-World Debugging

By
AMBA Protocol Series · Part 10 of 10 AXI Verification Interview Questions and Real-World Debugging Common protocol violations, how to read them off a waveform, and a curated set of interview questions with concise, correct answers — the capstone of the core 10-day series. AMBA Protocol Series: From APB & AHB to AXI — A Complete Guide for VLSI Engineers This wraps up the core 10-day series. Everything here draws directly on Days 1–9 — if any answer below feels unfamiliar, that's a good signal for which earlier post to revisit. (If you want to go further, see the 20-day extended list at the end of this post.) In This Article Common Protocol Violations Debugging From a Waveform Interview Questions and Answers Series Recap Extending the Series 1. Common Protocol Violations VALID deasserted before handshake — a source drops VALID before READY ever went high (violates the Day 8 stabi...
Post a Comment
Read more

Cache Basics and Cache Mapping Techniques

By
  Cache Basics and Cache Mapping Techniques  Modern processors execute billions of instructions every second. However, processor speed has increased much faster than main memory (RAM) speed. This difference, known as the memory wall , creates a performance bottleneck because the CPU often has to wait for data from slower memory. To solve this problem, computer systems use cache memory —a small, high-speed memory located between the CPU and the main memory. In this article, we will understand the fundamentals of cache memory, the principle of locality, cache organization, and the three major cache mapping techniques. What is Cache Memory? Cache memory is a small, high-speed memory that stores copies of frequently accessed data from the main memory. Since accessing cache is much faster than accessing RAM, the CPU first checks whether the required data is available in the cache. If the data is found in the cache, it is called a cache hit . Otherwise, the CPU fetches the dat...
Post a Comment
Read more

Timing Basics in Static Timing Analysis (STA): Delay Models, Sequential Timing, and Wire Delays

By
Timing Basics in Static Timing Analysis (STA) Static Timing Analysis (STA) is one of the most important verification techniques used in modern VLSI design. Before a chip is manufactured, engineers must verify that every signal reaches its destination within the required clock period. Even if a design passes functional simulation, it may still fail after fabrication because of timing violations. Unlike simulation, Static Timing Analysis mathematically analyzes every timing path without applying input test vectors. This makes STA significantly faster and capable of analyzing millions of timing paths efficiently. Table of Contents What is Static Timing Analysis? Why STA is Required Propagation Delay Contamination Delay Cell Delay Models Combinational Gate Delay Sequential Timing Setup Time Hold Time Wire Delay RC Delay Model PVT Corners Worked Examples Interview Questions Key Takeaways What is Static Timing Analysis? Static Ti...
Post a Comment
Read more

Computer Architecture Interview Question Part 1

By
Skip to content Computer Architecture Interview Series Part 1 · CPU Basics · RISC vs CISC · ISA 50 Most Asked Computer Architecture Interview Questions (Part 1) The foundational round every VLSI, ASIC, and CPU design interview opens with: instruction set architecture, RISC vs CISC trade-offs, Von Neumann vs Harvard design, registers, endianness, and the fetch-decode-execute cycle — explained the way interviewers actually expect you to answer.  40 Questions (Q1–Q40) ⌛ 22 min read  VLSI & Computer Architecture Interviews On this page Foundations of Computer Architecture RISC vs CISC — Core Differences Von Neumann, Harvard & the Semantic Gap Architecture Styles, Endianness & Registers ILP, VLIW, Superscalar & Amdahl's Law Register Files, Microcontrollers & the Fetch Cycle Tip...
Post a Comment
Read more