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Low Power Verification: Isolation Cells and State Retention Explained

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 Modern System-on-Chip (SoC) designs power down unused hardware blocks to reduce energy consumption. While power gating significantly reduces leakage power, it introduces new verification challenges. When one power domain is switched OFF while another remains active, invalid signals, unknown (X) values, and loss of register contents can cause functional failures.

To overcome these issues, designers use Isolation Cells and State Retention Cells. Low Power Verification (LPV) ensures these mechanisms are correctly implemented according to the Unified Power Format (UPF) specification.

This article explains why isolation and state retention are required, how they work, and what verification engineers must validate.


Why Do We Need Isolation and State Retention?

Power gating disconnects the supply voltage from selected logic blocks when they are idle.

Although this saves power, two major problems occur:

  • Outputs from the powered-down domain become invalid (X values).
  • Registers inside the powered-down domain lose their stored data.

These issues can corrupt the functionality of the entire SoC unless appropriate low-power structures are inserted.

Two important techniques solve these problems:

  • Isolation Cells
  • State Retention Cells

Isolation Cells

Isolation cells prevent invalid signals from propagating from a powered-down domain to an active domain.

Without isolation, outputs of a powered-off block become unknown (X). These unknown values may propagate through the design, causing simulation failures and unpredictable hardware behavior.

An isolation cell forces the output to a predefined value whenever the source power domain is OFF.

Typical clamp values are:

  • Clamp to logic 0
  • Clamp to logic 1

The power controller generates an ISO_EN signal that enables or disables the isolation cell.

Benefits of Isolation Cells

  • Prevent X propagation
  • Protect always-on logic
  • Improve system reliability
  • Ensure deterministic behavior during power transitions

Isolation Cell Operation

Consider two power domains:

  • PD_OFF (Switchable)
  • PD_ON (Always Active)

When PD_OFF is ON:

ISO_EN = 0

Signal passes normally.

When PD_OFF powers down:

ISO_EN = 1

Output becomes:

0 (Clamp-to-0)
or

1 (Clamp-to-1)

The destination domain therefore never receives unknown values.

State Retention

Power gating removes supply from registers.

A normal flip-flop immediately loses its contents after power is removed.

However, many applications require software execution or hardware state to continue exactly where it stopped after wake-up.

This is achieved using Retention Cells.

How Retention Cells Work

A retention register contains two storage elements:

  • Main flip-flop
  • Retention latch (powered by Always-On supply)

Before power-down:

SAVE signal asserted

The register contents are copied into the retention latch.

During power OFF:

  • Main flip-flop loses power
  • Retention latch remains powered
  • Data is safely stored

After power restoration:

RESTORE signal asserted

The stored value is copied back into the main register.

Execution resumes from the previous state.

Retention Implementation Methods

There are two common approaches.

Integrated Retention Flip-Flops

The retention latch is built inside the flip-flop.

Advantages:

  • Faster
  • Compact
  • Lower routing complexity

External Retention Memory

Dedicated retention RAM stores register values.

Advantages:

  • Scalable
  • Efficient for very large designs
  • Lower area for massive retention requirements

Isolation Architecture

A simplified isolation architecture consists of:



State Retention Architecture


A retention architecture consists of:

Only the retention storage remains powered while the main domain is switched OFF.










Power States and Control Signals

During power transitions, isolation and retention signals follow a defined sequence.

Power StateDomain PowerISO_ENRetention Action
ActiveON0None
Prepare for ShutdownON0SAVE
Powered DownOFF1Hold Saved State
RestoreON1RESTORE
Active AgainON0Normal Operation

Following this sequence prevents data corruption and functional failures.

What Should Verification Engineers Check?

Low Power Verification focuses on ensuring that the implemented design matches the UPF intent.

Typical verification checks include:

Isolation Verification

  • Isolation cells inserted on all required crossings
  • Correct isolation control signal connection
  • Proper clamp value
  • Isolation active only when source domain is OFF
  • No missing isolation cells

Retention Verification

  • Retention cells inserted where required
  • SAVE asserted before power-down
  • RESTORE asserted after power-up
  • Register values correctly restored
  • No corruption during power cycling

UPF Consistency

Verify that:

  • RTL implementation matches UPF
  • Isolation strategy is correctly applied
  • Retention strategy is correctly applied
  • Power intent matches physical implementation


Common Issues Found During Low Power Verification

Low power bugs are often difficult to detect without dedicated LPV flows.

Some common issues include:

IssueImpact
Missing isolation cellX propagation
Wrong isolation controlIsolation active at incorrect time
Incorrect clamp valueFunctional mismatch
Missing retention cellState loss after power cycle
Incorrect SAVE/RESTORE orderData corruption
Retention on unnecessary registersIncreased area and power
RTL and UPF mismatchDesign violates power intent

Low Power Verification Flow

A typical LPV flow consists of the following stages:

Step 1: Read UPF

Load the power intent describing domains, switches, isolation, and retention strategies.

Step 2: Connectivity Checks

Verify:

  • Isolation cell insertion
  • Retention cell insertion
  • Power switch connectivity
  • Control signal routing

Step 3: Structural Verification

Ensure:

  • Correct cell type
  • Correct placement
  • Proper clamp configuration

Step 4: Power-Aware Simulation

Run simulations with realistic power transitions to verify:

  • Domain shutdown
  • Wake-up
  • Isolation behavior
  • State retention
  • Reset interactions

Step 5: Assertions and Coverage

Add SystemVerilog Assertions (SVA) to verify:

  • Isolation active only during power OFF
  • SAVE before power-down
  • RESTORE after power-up
  • No X propagation

Collect functional coverage for:

  • Power state transitions
  • Isolation enable sequences
  • Retention save/restore scenarios

Step 6: Sign-Off

Confirm that RTL, UPF, structural checks, assertions, and simulation results all agree with the intended power architecture.

Best Practices for LPV

  • Define power intent early using UPF.
  • Verify isolation and retention before full-chip integration.
  • Ensure clamp values match the design specification.
  • Verify SAVE and RESTORE timing across all power modes.
  • Include power-aware simulations in regression.
  • Use assertions to catch sequencing errors.
  • Achieve comprehensive coverage of all power states and transitions.

Conclusion

As modern SoCs continue to adopt aggressive power-saving techniques, Isolation Cells and State Retention Cells have become fundamental building blocks of low-power design. Isolation cells prevent invalid signals from crossing between power domains, while retention cells preserve critical register contents across power cycles. However, simply inserting these structures is not enough—they must be thoroughly verified to ensure they operate correctly under all power conditions.

Low Power Verification combines structural checks, UPF validation, power-aware simulation, assertions, and coverage analysis to ensure that the implemented design faithfully follows the intended power architecture. By verifying isolation behavior, SAVE/RESTORE sequencing, clamp values, and power state transitions, engineers can eliminate elusive low-power bugs long before silicon.

A robust LPV methodology not only improves functional reliability but also enables faster wake-up, lower power consumption, and a more resilient SoC design ready for production.

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