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SoC Verification – Cache Coherency: Understanding MESI & MOESI Protocols

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SoC Verification – Cache Coherency: Understanding MESI & MOESI Protocols

Part of The Silicon Stack – SoC Verification Series

Modern System-on-Chips (SoCs) rarely contain just one processor. Today's smartphones, AI accelerators, networking chips, automotive controllers, and data center processors integrate multiple CPU cores, GPUs, DSPs, NPUs, and hardware accelerators that simultaneously access shared memory.

While multi-core architectures dramatically improve performance, they also introduce one of the most difficult verification challenges in semiconductor design:

How do we ensure that every processor always sees the correct value of shared data?

The answer lies in Cache Coherency Protocols, with MESI and MOESI being the most widely implemented protocols across modern processors.

For verification engineers, cache coherency is not just about validating cache states—it is about ensuring system correctness under millions of concurrent transactions occurring every second.

Why Cache Coherency is Needed

Each processor core contains one or more levels of cache (L1, L2, L3) to reduce memory access latency.

Consider two processor cores.


Suppose memory location X initially contains 10.

Memory[X] = 10

Both cores read X.

Core0 Cache = 10
Core1 Cache = 10

Now Core0 writes

X = 20

Without a coherency protocol,

Core0 Cache = 20
Core1 Cache = 10

Core1 still observes the old value.

This is called stale data, leading to incorrect software behavior, synchronization failures, and data corruption.

Cache coherency protocols eliminate this problem by ensuring that every core observes a consistent view of memory.

Cache Coherency Architecture

A simplified multi-core architecture looks like this:




Whenever one processor modifies shared data,

  • snoop messages are generated
  • other caches respond
  • cache states change
  • memory may be updated
  • ownership transfers between processors

All these operations must be verified thoroughly.

MESI Cache Coherency Protocol

MESI is one of the most common cache coherency protocols.

It defines four cache states.

M — Modified

  • Cache owns the only valid copy.
  • Memory contains stale data.
  • Dirty cache line. 
Memory : Old

Cache : New

E — Exclusive

  • Cache owns the only clean copy.
  • Memory already contains correct data.
  • No other cache has this line.

S — Shared

Multiple caches may contain the same data.

Core0 Cache
      \
       Shared Data
      /
Core1 Cache

Memory is also up-to-date.

I — Invalid

Cache line is no longer valid.

Any access requires fetching data again.

MESI State Transition

The protocol continuously transitions between these four states.

Every transition must follow protocol rules.

Typical MESI Transactions

Processor Read (PrRd)

If cache line is Invalid,

I → S

or

I → E

depending on whether another cache owns the block.

Processor Write (PrWr)

Writing to a shared block requires exclusive ownership.

S → M

after invalidating every other cache.

BusRd

Another processor requests shared data.

Modified owner writes data or supplies it.

M → S

BusRdX

Another processor requests exclusive ownership.

All other copies become Invalid.

S → I
M → I

Writeback

Dirty cache line is written to memory.

M → I

or

M → E

depending on implementation.

MESI Example

Consider two processors.

Initial state

Memory[X]=5

Core0 : I
Core1 : I

Step 1

Core0 reads X.

Core0 = E

Step 2

Core0 writes X.

Core0

E → M

Memory still contains old data.

Step 3

Core1 reads X.

A BusRd occurs.

Core0 supplies the latest data.

States become

Core0 : S

Core1 : S

Memory is updated if required.

MOESI Protocol

MOESI extends MESI by introducing one additional state:

Owned (O)

States become

  • Modified
  • Owned
  • Exclusive
  • Shared
  • Invalid

Owned State

Owned is the key difference between MESI and MOESI.

The cache owns dirty data while allowing other caches to read it.

Memory : Old

Core0 : Dirty Copy (Owner)

Core1 : Shared Copy

Instead of writing back immediately,

the owner directly supplies data to other processors.

Advantages include:

  • lower memory bandwidth
  • fewer writebacks
  • higher performance
  • improved scalability

MESI vs MOESI

FeatureMESIMOESI
States45
Dirty shared dataNoYes
Owned stateNoYes
Memory writebacksMoreFewer
PerformanceGoodBetter
ComplexityLowerHigher

MOESI is therefore preferred in many high-performance multicore processors.

Verification Challenges

Verifying cache coherency is considerably more difficult than verifying a single RTL module.

Multiple agents generate requests simultaneously.

Transactions overlap.

Responses arrive out of order.

Ownership continuously changes.

Corner cases become extremely complex.

Some common scenarios include:

  • simultaneous writes from multiple cores
  • read-after-write hazards
  • write-after-write hazards
  • dirty line eviction
  • ownership transfer
  • snoop races
  • cache flush operations
  • reset during transactions
  • concurrent invalidations
  • randomized interleaved traffic

These scenarios often expose subtle bugs that only appear under heavy concurrency.

UVM Verification Environment

A typical cache coherency verification environment contains multiple processor agents connected to the cache subsystem.

The environment generates concurrent traffic from multiple cores while checking protocol correctness in real time.

What Should Be Verified?

A robust verification plan should validate:

Cache State Transitions

Every legal MESI/MOESI transition must be exercised.

Snoop Responses

Verify that snoop requests receive the correct response from each cache.

Ownership Transfer

Only one cache may own dirty data at any instant.

Data Consistency

Every processor must observe the latest committed value.

Invalidation

Other cache copies must be invalidated whenever exclusive ownership is acquired.

Write Ordering

Writes must remain visible in the correct order across processors.

Deadlock

No transaction should stall indefinitely.

Livelock

Caches should always make forward progress.

Functional Coverage

Coverage should include:

  • every protocol state
  • every state transition
  • every bus transaction
  • every snoop type
  • concurrent accesses
  • race conditions
  • cache evictions
  • randomized traffic
  • reset scenarios

Protocol Checkers and Assertions

Assertions significantly improve verification quality.

Example properties include:

  • only one Modified owner exists
  • Shared data remains identical across caches
  • Invalid cache never returns data
  • writeback occurs before eviction of dirty data
  • exclusive ownership is granted correctly
  • BusRdX invalidates all other copies
  • no illegal state transitions occur

These assertions detect protocol violations immediately during simulation.

Common Bugs Found During Verification

Typical coherency bugs include:

  • Missing cache invalidation
  • Duplicate Modified owners
  • Lost writebacks
  • Incorrect snoop responses
  • Data mismatch across caches
  • Invalid ownership transfer
  • Race conditions under simultaneous requests
  • Deadlock during heavy traffic
  • Livelock due to arbitration
  • Incorrect eviction of dirty cache lines

Many of these issues only appear after running millions of randomized transactions, making constrained-random verification and functional coverage essential.

Best Verification Practices

Successful cache coherency verification combines multiple methodologies:

  • Develop a comprehensive verification plan covering all protocol states and transitions.
  • Use constrained-random stimulus to generate diverse multi-core traffic patterns.
  • Implement protocol assertions to detect illegal behavior immediately.
  • Build a golden reference model for coherency checking.
  • Measure functional coverage to ensure every scenario has been exercised.
  • Stress-test the design with long randomized regression runs.
  • Analyze waveforms alongside transaction logs to debug complex protocol interactions.
  • Verify corner cases such as simultaneous requests, cache evictions, resets, and heavy contention.

Conclusion

Cache coherency forms the foundation of every modern multicore SoC. Protocols such as MESI and MOESI ensure that all processors maintain a consistent view of shared memory, enabling reliable parallel execution.

From a verification perspective, coherency is one of the most demanding domains in ASIC verification. Engineers must validate protocol state transitions, snoop behavior, ownership transfers, write ordering, and data consistency across numerous concurrent scenarios. Achieving confidence requires a combination of constrained-random verification, protocol assertions, reference models, scoreboards, and comprehensive functional coverage.

Mastering cache coherency verification is a valuable skill for any ASIC or SoC verification engineer, especially as multicore processors, AI accelerators, and high-performance computing systems continue to grow in complexity.

Key Takeaways

  • Cache coherency ensures all processor cores observe a consistent view of shared memory.
  • MESI defines four states: Modified, Exclusive, Shared, and Invalid.
  • MOESI extends MESI with an Owned state, reducing memory writebacks and improving performance.
  • Verification must cover state transitions, snoop responses, invalidations, ownership transfers, and concurrent multi-core traffic.
  • Protocol assertions, scoreboards, reference models, and functional coverage are essential for achieving robust cache coherency verification.
  • Cache coherency remains one of the most challenging and rewarding areas of modern SoC verification.

Next in the SoC Verification Series: Cache Controller Verification – Architecture, UVM Environment, Test Plan, Assertions, and Functional Coverag

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