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Understanding a Real GPU Architecture

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Understanding a Real GPU Architecture (NVIDIA Ampere GA100)

After learning about GPU fundamentals over the past few days, it's time to connect everything together. Instead of studying individual components in isolation, today we'll explore how a real GPU is organized and how all of its hardware blocks work together to deliver massive computing power.

For this study, we'll use NVIDIA's Ampere GA100, one of the world's most advanced data-center GPUs designed for AI, HPC (High Performance Computing), and scientific simulations.



Why Study a Real GPU?

Learning CUDA cores, memory hierarchy, Tensor Cores, and warp scheduling individually is useful—but understanding how they interact inside a real GPU provides a much clearer picture of GPU architecture.

A real GPU is essentially a collection of specialized hardware blocks working simultaneously to execute thousands of operations in parallel.

The GA100 architecture demonstrates how NVIDIA balances:

  • Massive parallel computation
  • Extremely high memory bandwidth
  • Efficient scheduling
  • Low-latency communication
  • AI acceleration

Overall Architecture of the GA100



Together, these components keep the GPU continuously supplied with data while maximizing compute utilization.

Graphics Processing Clusters (GPCs)

The GPU chip is divided into multiple Graphics Processing Clusters (GPCs).

Each GPC acts like a mini GPU inside the larger chip.

A GPC contains several:

  • Texture Processing Clusters (TPCs)
  • Rasterization hardware (graphics workloads)
  • Multiple Streaming Multiprocessors (SMs)

This modular design allows workloads to be distributed efficiently across the chip.

Think of a GPC as a department inside a large company, where each department has multiple teams working independently.

Texture Processing Clusters (TPCs)

Inside every GPC are multiple Texture Processing Clusters.

A TPC groups together one or more Streaming Multiprocessors.

Its responsibilities include:

  • Organizing SM resources
  • Texture processing
  • Graphics-specific operations
  • Forwarding work to SMs

Although originally designed for graphics, TPCs also help organize compute workloads efficiently.

Streaming Multiprocessor (SM): The Heart of the GPU

The Streaming Multiprocessor (SM) is where actual computation happens.

Every SM contains several specialized hardware units working simultaneously.

These include:

  • Warp Scheduler
  • Dispatch Unit
  • Register File
  • CUDA Cores
  • Tensor Cores
  • Load/Store Units
  • Shared Memory
  • L1 Cache

Each SM executes thousands of lightweight threads by grouping them into warps of 32 threads.

Warp Scheduler

The Warp Scheduler is responsible for deciding which warp should execute next.

Every clock cycle it:

  • Checks which warps are ready
  • Selects eligible warps
  • Issues instructions to execution units

If one warp is waiting for memory, another ready warp can immediately execute.

This hardware scheduling is one of the biggest reasons GPUs achieve such high throughput.

Register File

Registers are the fastest storage inside the GPU.

Each thread owns its own registers, allowing immediate access to frequently used variables.

Advantages include:

  • Lowest latency
  • Highest bandwidth
  • No contention between threads

Since registers are limited, efficient register usage is essential for maximizing GPU occupancy.

CUDA Cores

CUDA Cores are the primary arithmetic units of NVIDIA GPUs.

They execute operations such as:

  • Integer arithmetic
  • Floating-point arithmetic
  • Logical operations
  • Address calculations

Thousands of CUDA cores work in parallel across all SMs, enabling enormous computational throughput.

Tensor Cores

Tensor Cores are dedicated AI accelerators introduced to speed up matrix operations.

They perform matrix multiplication and accumulation much faster than traditional CUDA cores.

Tensor Cores support multiple data types, including:

  • FP16
  • BF16
  • TF32
  • INT8
  • FP32 accumulation

These specialized units are responsible for the incredible training and inference performance of modern AI systems.

Load/Store Units

Load/Store Units move data between registers and memory.

Their responsibilities include:

  • Reading data from memory
  • Writing results back
  • Accessing Shared Memory
  • Handling memory requests efficiently

Without these units, computation would frequently stall waiting for data.

L1 Cache and Shared Memory

Each Streaming Multiprocessor includes:

  • L1 Cache
  • Shared Memory

These two memories share hardware resources and can be configured depending on the application.

They provide:

  • Very low latency
  • High bandwidth
  • Fast communication between threads in the same block

Many CUDA optimizations focus on maximizing Shared Memory usage.

Memory Hierarchy

The GPU memory system follows a hierarchy where smaller memories are faster and larger memories are slower.

From fastest to slowest:

  1. Registers
  2. Shared Memory / L1 Cache
  3. L2 Cache
  4. HBM2e Global Memory
  5. CPU Host Memory

As data moves closer to the SM:

  • Latency decreases
  • Bandwidth increases
  • Capacity becomes smaller

Understanding this hierarchy is essential for writing high-performance GPU programs.

High-Bandwidth Memory (HBM2e)

The GA100 uses HBM2e, one of the fastest memory technologies available.

Compared to conventional GDDR memory, HBM provides:

  • Extremely high bandwidth
  • Lower power consumption
  • Shorter communication distance
  • Better performance for AI workloads

High-bandwidth memory ensures Tensor Cores remain continuously supplied with data.

L2 Cache

The L2 Cache is shared across the entire GPU.

It acts as an intermediate buffer between HBM and all Streaming Multiprocessors.

Benefits include:

  • Reduced memory latency
  • Lower HBM traffic
  • Better data reuse
  • Improved overall performance

NVLink

Modern AI training often requires multiple GPUs working together.

NVLink provides a high-speed communication path directly between GPUs.

Advantages include:

  • Lower latency than PCIe
  • Higher bandwidth
  • Faster data sharing
  • Better scalability

Large AI clusters rely heavily on NVLink to exchange model parameters efficiently.

Copy Engines (DMA)

Copy Engines, also known as DMA engines, move data independently of the compute units.

Instead of forcing CUDA cores to wait during memory transfers, DMA performs transfers in the background.

This allows:

  • Data transfer and computation to overlap
  • Higher GPU utilization
  • Reduced idle time

Efficient data movement is just as important as fast computation.

GPU Compute Flow

A typical computation follows these steps:

  1. Input data is stored in HBM.
  2. Data moves through the cache hierarchy into Shared Memory.
  3. Streaming Multiprocessors execute kernels using CUDA and Tensor Cores.
  4. Results are written back to HBM.
  5. The process repeats for thousands of thread blocks until the workload is complete.

This pipeline keeps the GPU busy while minimizing memory bottlenecks.

Key Highlights of NVIDIA Ampere GA100

Some notable features of the GA100 architecture include:

  • Up to 108 Streaming Multiprocessors
  • Up to 69 TFLOPS FP32 performance
  • Third-generation Tensor Cores
  • Second-generation RT Cores
  • Up to 2 TB/s HBM2e memory bandwidth
  • Large 40 MB L2 Cache
  • High-speed NVLink interconnect
  • Support for Multi-Instance GPU (MIG), allowing one GPU to be partitioned into multiple isolated instances

These innovations make the GA100 one of the most powerful GPUs for AI, machine learning, and scientific computing.

Final Thoughts

A GPU is much more than thousands of CUDA cores. Its true performance comes from the seamless coordination of compute units, memory hierarchy, scheduling hardware, and high-speed interconnects.

The NVIDIA Ampere GA100 demonstrates how modern GPU design balances parallel computation with efficient data movement. Every hardware block—from HBM2e and L2 Cache to Warp Schedulers, Tensor Cores, and NVLink—plays a critical role in keeping the GPU operating at peak performance.

Understanding this architecture provides a strong foundation for learning CUDA programming, GPU optimization, AI accelerators, and modern computer architecture.




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