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AHB Protocol Explained: Architecture, Signals and Transfers

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AMBA Protocol Series · Part 4 of 10

AHB Protocol Explained: Architecture, Signals and Transfers


Master/slave architecture, pipelined address and data phases, HREADY, HRESP, and burst transfer types — the mid-performance backbone that came before AXI.

AMBA Protocol Series: From APB & AHB to AXI — A Complete Guide for VLSI Engineers

AHB introduced the idea that made all later high-performance AMBA protocols possible: pipelining. While one transaction's data phase is completing, the next transaction's address phase can already be underway. It's a single shared bus, so only one transaction is in flight at a time — but overlapping address and data phases still meaningfully increases throughput over APB's fully sequential model.

In This Article

  1. Master/Slave Topology and the Arbiter
  2. Key AHB Signals
  3. Address and Data Phase Pipelining
  4. HREADY and HRESP
  5. Burst Transfer Types
  6. Transaction Walkthrough
  7. Recap

1.Master/Slave Topology and the Arbiter

Unlike APB, AHB supports multiple masters (e.g., CPU, DMA controller) sharing the same bus. Since only one master can drive the address/data bus at a time, an arbiter grants bus ownership one master at a time, based on each master's HBUSREQ request and a configurable priority/round-robin scheme. A central decoder uses the address to generate the correct HSELx for the target slave.

2.Key AHB Signals

SignalDriven ByPurpose
HADDRMasterTransfer address
HTRANSMasterTransfer type: IDLE, BUSY, NONSEQ, SEQ
HWRITEMaster1 = write, 0 = read
HSIZEMasterTransfer size (byte/halfword/word...)
HBURSTMasterBurst type and length (SINGLE, INCR4, WRAP8...)
HWDATA / HRDATAMaster / SlaveWrite / read data buses
HREADYSlave1 = previous transfer complete, bus ready for next address phase
HRESPSlaveOKAY, ERROR, RETRY, or SPLIT response

3.Address and Data Phase Pipelining

Every AHB transfer has two phases: an address phase (one cycle, where HADDR/HTRANS/HWRITE/HSIZE are driven) and a data phase (one or more cycles, extended by HREADY). Pipelining means the address phase of transfer N+1 happens during the data phase of transfer N — the two overlap rather than running strictly back-to-back, which is what makes AHB faster than APB despite still sharing a single bus.

4.HREADY and HRESP

HREADY, driven by the currently selected slave, is the single most important control signal on AHB. When low, it stalls the entire bus — extending the current data phase and freezing the next transfer's address phase from advancing. When high, the current data phase completes and the pipeline advances.

HRESP reports the transfer status once HREADY finally goes high: OKAY (success), ERROR (failed transfer, master must decide how to respond), RETRY and SPLIT (used by slaves needing to release the bus temporarily while completing a slow access — an advanced, less commonly implemented feature).

⚠️ Common Design Mistake
A slave that asserts HRESP = ERROR must still assert it for two consecutive cycles (with HREADY low on the first, then high on the second) per the AHB spec, so the master has time to correctly detect and act on the error before the pipeline advances.

5.Burst Transfer Types

HBURST ValueMeaning
SINGLESingle transfer, not part of a burst
INCRIncrementing burst of undefined length
WRAP4 / INCR44-beat wrapping or incrementing burst
WRAP8 / INCR88-beat wrapping or incrementing burst
WRAP16 / INCR1616-beat wrapping or incrementing burst

WRAP bursts are address-aligned and wrap back to the start of the aligned block once they hit the boundary — useful for cache-line-fill traffic, where the critical word can be fetched first.

6.Transaction Walkthrough

AHB Single Write, No Wait States // Address phase (cycle 1) HADDR = 0x1000_0004, HTRANS = NONSEQ, HWRITE = 1, HSIZE = word // Data phase (cycle 2) — overlaps with next address phase if back-to-back HWDATA = 0xCAFEF00D HREADY = 1 // slave signals completion, HRESP = OKAY

Recap: What We Covered Today

  • AHB supports multiple masters through a central arbiter; only one transaction is in flight on the shared bus at a time.
  • Address and data phases pipeline: the next address phase overlaps the current data phase.
  • HREADY (from the slave) stalls or advances the entire bus; HRESP reports OKAY/ERROR/RETRY/SPLIT.
  • HBURST defines INCR (incrementing) and WRAP (wrapping) burst types of fixed lengths.
Coming Up — Day 5

AXI4 Protocol Explained: The Complete Beginner's Guide

Tomorrow we move into AXI4: the five independent channels, the VALID/READY handshake that governs every one of them, and why this architecture removes AHB's single-shared-bus bottleneck.

◀ Day 3: APB Protocol Day 4 of 10 Day 5: AXI4 Protocol ▶
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