Skip to main content

AMBA Protocol Family: AXI, AHB, APB and ACE Explained

Image
By
AMBA Protocol Series · Part 2 of 10

AMBA Protocol Family: AXI, AHB, APB and ACE Explained



A closer look at each major member of the AMBA family — what problem it was built to solve, where it sits in an SoC, and how AXI, AHB, APB, and ACE relate to one another before we go signal-by-signal starting Day 3.

AMBA Protocol Series: From APB & AHB to AXI — A Complete Guide for VLSI Engineers

On Day 1, we established that AMBA is a family of specifications, not a single protocol, and walked through its evolution from 1996 to today. Now we zoom into the four protocols you'll actually encounter in day-to-day RTL design, verification, and interviews: APB, AHB, AXI, and ACE. Each one exists because the others weren't a good fit for a particular kind of block.

In This Article

  1. APB: The Peripheral Bus
  2. AHB: The System Bus
  3. AXI: The High-Performance Interface
  4. ACE: Adding Cache Coherency
  5. Side-by-Side Comparison
  6. Choosing the Right Protocol for a Block
  7. Recap

1.APB: The Peripheral Bus

APB (Advanced Peripheral Bus) is the simplest protocol in the AMBA family, and that simplicity is the entire point. It was designed for low-bandwidth, low-power peripherals where the priority is minimal gate count and ease of design — not throughput.

  • Typical devices: UART, SPI, I2C, GPIO, timers, watchdogs, control/status register blocks.
  • Transfer style: Non-pipelined — one transfer completes fully before the next begins.
  • Bus topology: Single shared bus with one bridge/controller and multiple peripheral slaves; there's no concept of multiple APB masters.
  • Why it stays simple: These peripherals rarely need to move large amounts of data quickly, so paying for AXI-level complexity (multiple channels, burst logic, out-of-order completion) would only add area and power for no real benefit.

We'll go fully signal-level on APB, including its state machine (IDLE → SETUP → ACCESS), on Day 3.

2.AHB: The System Bus

AHB (Advanced High-performance Bus) sits a tier above APB. It was designed as the main system backbone in AMBA 2 era SoCs — connecting the CPU, on-chip memory, and DMA controllers with enough bandwidth for real system traffic, while still being far simpler than AXI.

  • Typical devices: On-chip SRAM, simpler memory controllers, DMA engines, and — via bridges — the APB domain.
  • Transfer style: Pipelined address and data phases, with burst support (INCR, WRAP).
  • Bus topology: A single shared address/data bus with multiplexor-based arbitration between multiple masters — only one transaction is "in flight" on the bus at a time, even though phases can overlap.
  • Where it's still used: Smaller microcontroller-class SoCs, and as a mid-tier bridge domain in larger chips between AXI and APB.

Full signal-level AHB — including HREADY, HRESP, and burst types — is Day 4.

3.AXI: The High-Performance Interface

AXI (Advanced eXtensible Interface) is what most modern high-performance SoC interconnects are built on. It was introduced specifically to remove AHB's single-shared-bus bottleneck by splitting a transaction into five independent channels:

  • Write Address (AW)
  • Write Data (W)
  • Write Response (B)
  • Read Address (AR)
  • Read Data (R)

Because these channels are independent, AXI supports multiple outstanding transactions, out-of-order completion (via transaction IDs), and much higher achievable bandwidth than AHB — at the cost of more verification complexity, which is exactly why AXI dominates verification interview questions.

🎯 Why This Matters for Verification
Every one of AXI's five channels uses its own independent VALID/READY handshake. That means a large share of AXI verification effort — and a large share of AXI interview questions — is about getting the interaction between channels right: address-before-data ordering, ID-based response matching, and outstanding transaction tracking.

We spend three full days on AXI: the architecture and handshake fundamentals on Day 5, the AXI4 / AXI4-Lite / AXI-Stream comparison on Day 6, and burst/address calculation on Day 7.

4.ACE: Adding Cache Coherency

ACE (AXI Coherency Extensions) extends AXI4 with the additional signaling needed for hardware cache coherency across multiple CPU clusters. In a multi-core system, each core may cache the same memory location — ACE defines the snoop channels and coherency states (based on the MOESI-style model) that let those caches stay consistent without software intervention.

ACE is beyond this series' beginner-to-intermediate scope, but it's worth knowing conceptually: it's the reason a write from Core A can be correctly "seen" by Core B's cache without an explicit flush, and it's the direct ancestor of CHI, AMBA 5's coherency protocol for even larger multi-core systems.

5.Side-by-Side Comparison

AspectAPBAHBAXI4
ChannelsSingle, sharedSingle, shared (pipelined)5 independent channels
Outstanding transactions1 (no pipelining)Limited (bus-level pipelining only)Multiple, ID-tagged
Burst supportNoYes (fixed set of burst types)Yes (INCR, WRAP, FIXED)
Typical useLow-speed peripheralsMid-tier system busHigh-performance CPU/GPU/memory interconnect
Verification complexityLowMediumHigh

6.Choosing the Right Protocol for a Block

A useful rule of thumb when reading — or designing — an SoC block diagram: match the protocol to the block's actual bandwidth and latency requirements, not the other way around.

  • Does the block move large bursts of data at high frequency, and can it tolerate out-of-order completion? → AXI
  • Does it need moderate bandwidth with simple, in-order pipelined access? → AHB
  • Is it a low-speed control/status interface where simplicity and low power matter more than throughput? → APB
  • Does it need to maintain cache coherency with other CPU clusters? → ACE (or CHI, for larger systems)
📌 Note
In practice, a single SoC uses several of these at once, connected through bridges — exactly as shown in the interconnect hierarchy diagram from Day 1. Recognizing which protocol belongs where is itself a common system-design interview question.

Recap: What We Covered Today

  • APB is the simple, non-pipelined protocol for low-speed peripherals.
  • AHB is a pipelined, burst-capable system bus, but still uses a single shared address/data bus.
  • AXI splits transactions into 5 independent channels, enabling multiple outstanding, out-of-order transactions and much higher throughput.
  • ACE extends AXI4 with cache-coherency signaling for multi-core coherent systems.
  • Real SoCs combine all of these, matched to each block's actual performance needs.
Coming Up — Day 3

APB Protocol Explained with Example

Tomorrow we go fully signal-level on APB: architecture, every signal, the IDLE/SETUP/ACCESS state machine, and a complete read and write transaction walkthrough.

◀ Day 1: AMBA Beginner's Guide Day 2 of 10 Day 3: APB Protocol ▶
Labels:

Comments

Post a Comment

Popular posts from this blog

Module 1 — SystemVerilog Basics

By
VLSI Verification  •  SystemVerilog Series Module 1 — SystemVerilog Basics A complete, example-driven walkthrough of SystemVerilog fundamentals: data types, variables vs nets, arrays of every flavor, strings, enums, structs, unions, and typedef — the building blocks every verification engineer needs before UVM. 🧩 Beginner → Intermediate ⏱ ~25 min read 💻 Code Examples Included 📑 Table of Contents Introduction to SystemVerilog Verilog vs SystemVerilog Data Types: 2-State vs 4-State Logic Variables and Nets Arrays: Packed vs Unpacked Dynamic Arrays Queues Associative Arrays Strings Enumerations Structures Unions Typedef 1 Introduction to SystemVerilog SystemVerilog (IEEE 1800) is a unified hardware description and verification language (HDVL). It extends Verilog (IEEE 1364) with powerful constructs for design (interfaces, always_comb/always_ff, enhanced d...
Post a Comment
Read more

GPU Memory System & Interconnect: How Data Travels Inside a Modern GPU

By
GPU Memory System & Interconnect: How Data Travels Inside a Modern GPU Modern GPUs deliver incredible computing power by processing thousands of operations simultaneously. While compute cores often receive the spotlight, the real performance of a GPU depends heavily on how efficiently data moves between memory and compute units. A GPU memory system is designed to provide extremely high bandwidth while keeping latency as low as possible. This is achieved through a collection of specialized hardware components working together, including the Memory Controller, HBM/GDDR memory, Crossbar, Network-on-Chip (NoC), DMA Engine, PCIe Interface, and NVLink. In this article, we'll explore each component in detail and understand how they collectively enable high-performance parallel computing. Why Does GPU Memory Matter? Every GPU application—from gaming and graphics rendering to AI model training and scientific simulations—requires continuous movement of enormous amounts of data. For examp...
Post a Comment
Read more

Clock Domain Crossing (CDC): A Complete Beginner's Guide to Metastability, Synchronizers & Safe Data Transfer

By
Clock Domain Crossing (CDC): A Complete Beginner's Guide to Metastability, Synchronizers & Safe Data Transfer Modern System-on-Chip (SoC) designs rarely operate with a single clock. Instead, different modules such as CPUs, GPUs, memory controllers, communication interfaces, and peripherals often run at different clock frequencies or even use completely independent clock sources . When data moves from one clock domain to another, timing uncertainty can cause serious problems such as metastability , data corruption , and unpredictable system behaviour . This challenge is known as Clock Domain Crossing (CDC) . CDC is one of the most important topics in ASIC Design , RTL Design , ASIC Verification , FPGA Design , and SoC Architecture . Every modern chip—from smartphones to automotive processors—uses CDC techniques to ensure reliable communication between multiple clock domains. In this article, we'll explore CDC fundamentals, metastability, synchronization techniques, asynchro...
Post a Comment
Read more

AXI Verification Interview Questions and Real-World Debugging

By
AMBA Protocol Series · Part 10 of 10 AXI Verification Interview Questions and Real-World Debugging Common protocol violations, how to read them off a waveform, and a curated set of interview questions with concise, correct answers — the capstone of the core 10-day series. AMBA Protocol Series: From APB & AHB to AXI — A Complete Guide for VLSI Engineers This wraps up the core 10-day series. Everything here draws directly on Days 1–9 — if any answer below feels unfamiliar, that's a good signal for which earlier post to revisit. (If you want to go further, see the 20-day extended list at the end of this post.) In This Article Common Protocol Violations Debugging From a Waveform Interview Questions and Answers Series Recap Extending the Series 1. Common Protocol Violations VALID deasserted before handshake — a source drops VALID before READY ever went high (violates the Day 8 stabi...
Post a Comment
Read more

Cache Basics and Cache Mapping Techniques

By
  Cache Basics and Cache Mapping Techniques  Modern processors execute billions of instructions every second. However, processor speed has increased much faster than main memory (RAM) speed. This difference, known as the memory wall , creates a performance bottleneck because the CPU often has to wait for data from slower memory. To solve this problem, computer systems use cache memory —a small, high-speed memory located between the CPU and the main memory. In this article, we will understand the fundamentals of cache memory, the principle of locality, cache organization, and the three major cache mapping techniques. What is Cache Memory? Cache memory is a small, high-speed memory that stores copies of frequently accessed data from the main memory. Since accessing cache is much faster than accessing RAM, the CPU first checks whether the required data is available in the cache. If the data is found in the cache, it is called a cache hit . Otherwise, the CPU fetches the dat...
Post a Comment
Read more

Timing Basics in Static Timing Analysis (STA): Delay Models, Sequential Timing, and Wire Delays

By
Timing Basics in Static Timing Analysis (STA) Static Timing Analysis (STA) is one of the most important verification techniques used in modern VLSI design. Before a chip is manufactured, engineers must verify that every signal reaches its destination within the required clock period. Even if a design passes functional simulation, it may still fail after fabrication because of timing violations. Unlike simulation, Static Timing Analysis mathematically analyzes every timing path without applying input test vectors. This makes STA significantly faster and capable of analyzing millions of timing paths efficiently. Table of Contents What is Static Timing Analysis? Why STA is Required Propagation Delay Contamination Delay Cell Delay Models Combinational Gate Delay Sequential Timing Setup Time Hold Time Wire Delay RC Delay Model PVT Corners Worked Examples Interview Questions Key Takeaways What is Static Timing Analysis? Static Ti...
Post a Comment
Read more

Computer Architecture Interview Question Part 1

By
Skip to content Computer Architecture Interview Series Part 1 · CPU Basics · RISC vs CISC · ISA 50 Most Asked Computer Architecture Interview Questions (Part 1) The foundational round every VLSI, ASIC, and CPU design interview opens with: instruction set architecture, RISC vs CISC trade-offs, Von Neumann vs Harvard design, registers, endianness, and the fetch-decode-execute cycle — explained the way interviewers actually expect you to answer.  40 Questions (Q1–Q40) ⌛ 22 min read  VLSI & Computer Architecture Interviews On this page Foundations of Computer Architecture RISC vs CISC — Core Differences Von Neumann, Harvard & the Semantic Gap Architecture Styles, Endianness & Registers ILP, VLIW, Superscalar & Amdahl's Law Register Files, Microcontrollers & the Fetch Cycle Tip...
Post a Comment
Read more