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AMBA Protocol Handshake: VALID and READY Explained

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AMBA Protocol Series · Part 8 of 10

AMBA Protocol Handshake: VALID and READY Explained


The exact handshake rules, timing requirements, backpressure behavior, and the design mistakes that cause the majority of real-world AXI protocol violations.

AMBA Protocol Series: From APB & AHB to AXI — A Complete Guide for VLSI Engineers

We introduced VALID/READY on Day 5, but the handshake has a small set of precise rules that RTL designers violate surprisingly often — and that verification engineers are expected to check with protocol assertions (which we'll formalize on Day 18). This post is the definitive reference for those rules.

In This Article

  1. The Basic Handshake Rule
  2. Rule: VALID Must Not Wait for READY
  3. Rule: VALID Cannot Be Deasserted Before the Transfer
  4. Backpressure: What READY Actually Controls
  5. Common Design Mistakes
  6. Recap

1.The Basic Handshake Rule

A transfer on any AXI channel occurs on the rising clock edge where both VALID (driven by the source) and READY (driven by the destination) are sampled high at the same time. Neither signal alone means anything — it's the AND of both that defines a completed beat.

2.Rule: VALID Must Not Wait for READY

The AXI specification explicitly forbids a source from waiting to see READY asserted before it asserts VALID. This rule exists to prevent a combinational deadlock: if the source waits for READY and the destination waits for VALID before responding, neither signal ever goes high and the bus locks up permanently.

🚫 Deadlock Pattern to Avoid
If your RTL combinationally derives VALID from READY (e.g., assign AWVALID = AWREADY;) or vice versa in a way that creates a dependency loop, you have a classic AXI deadlock bug. VALID must be generated independently of the current cycle's READY.

READY, in contrast, is allowed to depend on VALID — a destination can legally wait to see VALID before deciding to assert READY. The restriction is one-directional.

3.Rule: VALID Cannot Be Deasserted Before the Transfer

Once a source asserts VALID, it must hold it high — along with all associated data/control signals stable — until the cycle where READY is also sampled high and the transfer actually completes. VALID cannot be withdrawn "because it's taking too long," and the data behind it cannot change mid-wait.

READY has no equivalent restriction: a destination is free to assert and deassert READY on any cycle, whether or not VALID is currently high.

4.Backpressure: What READY Actually Controls

READY is how a slower consumer signals a faster producer to pause. In practice:

  • A FIFO-backed slave typically drives READY based on available buffer space — deasserting it when the FIFO is full.
  • A master reading from a slow memory might deassert ARREADY... wait, ARREADY is actually the slave's signal on the AR channel; the master would deassert RREADY if its own receive buffer is full.
  • Backpressure can propagate: a full downstream buffer causes an upstream block to deassert its own READY, which cascades further upstream — this is exactly how flow control works across a chain of AXI-Stream blocks too.
Legal Handshake Sequence — Slave Adds Wait States // Cycle 1: master asserts VALID, address/data stable, slave not ready yet AWVALID = 1, AWADDR = 0x2000, AWREADY = 0 // Cycle 2: still waiting — AWADDR MUST remain 0x2000, unchanged AWVALID = 1, AWADDR = 0x2000, AWREADY = 0 // Cycle 3: slave finally asserts ready — transfer completes this cycle AWVALID = 1, AWADDR = 0x2000, AWREADY = 1

5.Common Design Mistakes

  • Combinational VALID-READY loops — the deadlock pattern described above.
  • Changing data/control signals while VALID is asserted but READY hasn't arrived yet — a frequent RTL bug, especially when the data comes from a mux that's also being updated by unrelated logic.
  • Deasserting VALID after asserting it, before the transfer completes — often introduced accidentally when a state machine resets a "request pending" flag on the wrong condition.
  • Forgetting that WLAST/RLAST must align exactly with the final data beat — an off-by-one error here silently corrupts burst boundaries.

Recap: What We Covered Today

  • A transfer happens when VALID and READY are both sampled high on the same edge.
  • VALID must never wait for READY (prevents deadlock); READY may legally wait for VALID.
  • Once asserted, VALID and its accompanying signals must stay stable and high until the transfer completes.
  • READY implements backpressure and can be asserted/deasserted freely by the destination.
Coming Up — Day 9

AMBA Protocol Verification Using UVM

Tomorrow we shift from RTL to verification: building a UVM environment around an AMBA VIP — driver, monitor, scoreboard, assertions, functional coverage, and representative testcases.

◀ Day 7: AXI Burst Transactions Day 8 of 10 Day 9: AMBA Verification with UVM ▶
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