Skip to main content

ANALOG DESIGN BLOG 3 — SINGLE-STAGE & DIFFERENTIAL AMPLIFIERS

Image
By
Analog Design Series — Blog 3 of 7

Single-Stage & Differential Amplifiers


CS, CG, CD, cascode stages, and the differential pair — the core building blocks of analog ICs

1. Common-Source (CS) Amplifier

The CS stage is the workhorse amplifier in analog CMOS — high gain, high input impedance, and moderate bandwidth.

VDD │ [R_D] or [PMOS load] │ ├── V_out │ [M1] ← input at gate │ GND

Small-Signal Parameters

Av = −gm(RD ∥ ro) | Rin = ∞ | Rout = RD ∥ ro

With an active PMOS load (current source), the gain becomes:

Av = −gm1(ro1 ∥ ro2)
📘 Bandwidth Limitation

The dominant pole is at the output node: f-3dB = 1/(2π·Rout·Cout), where Cout includes Cdb, load capacitance, and Miller-multiplied Cgd. The gain-bandwidth product is approximately gm/(2π·Cout).

2. CS with Source Degeneration

Adding a resistor (or un-bypassed current source) in the source path trades gain for linearity and bandwidth.

Av = −gmRD / (1 + gmRS) ≈ −RD/RS (when gmRS ≫ 1)
ParameterWithout RSWith RS
Voltage gain−gmRD−gmRD/(1+gmRS)
LinearityPoor (depends on gm)Good (gain set by R ratio)
Input impedance∞∞
Output impedanceRDRD
BandwidthNarrowerWider (pole shifts up)
💡 Design Insight

Source degeneration is the MOSFET equivalent of emitter degeneration in BJTs. It implements local negative feedback, linearizing the VGS-to-ID relationship.

3. Common-Gate (CG) Amplifier

The CG stage has the input at the source and output at the drain. Gate is AC-grounded.

Av = +gm(RD ∥ ro) | Rin = 1/gm | Rout = RD ∥ ro

Key characteristics: non-inverting, low input impedance (1/gm), excellent high-frequency behavior (no Miller effect on Cgd).

📘 Where It Shines

The CG is used as: (1) a cascode device stacked on a CS stage, (2) a wideband input stage for current-mode signals, (3) a transimpedance amplifier input for photodiode receivers. Its low Rin provides 50Ω matching for RF applications.

4. Common-Drain (Source Follower)

The source follower provides voltage buffering — near-unity gain with high input impedance and low output impedance.

Av = gm(RS ∥ ro) / [1 + gm(RS ∥ ro)] ≈ gm/(gm + gmb) ≈ 0.8–0.9
Rout = 1/(gm + gmb) ∥ ro ≈ 1/gm
⚠️ Body Effect Penalty

In a source follower, the source rides with the signal, so VSB changes → Vth changes → gain drops below unity. The body transconductance gmb acts as negative feedback, reducing gain to gm/(gm+gmb). PMOS followers in an n-well process can eliminate this by tying the body to the source.

5. Cascode Amplifier

The cascode combines a CS input stage (M1) with a CG stage (M2) to achieve very high gain and high output resistance without the Miller effect.

VDD │ [Load] │ ├── V_out │ [M2] ← CG (gate AC-grounded via V_bias) │ [M1] ← CS (input at gate) │ GND
Av = −gm1(Rout,cascode ∥ Rload) where Rout,cascode = gm2ro2ro1

With a cascode PMOS load, the gain becomes:

Av = −gm1 × [gm2ro2ro1 ∥ gm4ro4ro3] ≈ −(gmro)² / 2
💡 Telescopic vs Folded Cascode

Telescopic: All transistors in a single stack. Highest speed, lowest noise, but limited output swing (VDD − 4VOV − 2Vth). Folded cascode: Input pair and cascode are in separate current branches. Better swing (VDD − 4VOV), wider input common-mode range, but more current consumption and added noise from folding transistors.

6. The Differential Pair

The MOS differential pair is the input stage of virtually every op-amp, comparator, and data converter.

VDD VDD │ │ [R_D1] [R_D2] │ │ ├─ V_out- ├─ V_out+ │ │ [M1]──────── [M2] │ gates │ └──────┬──────┘ [I_SS] ← tail current source │ GND

Differential-Mode Gain

Adm = −gm × RD (each half-circuit is a CS amplifier)

Common-Mode Gain

Acm = −RD / (2RSS) where RSS = ro of tail source

Linear Input Range

The differential pair steers current linearly for small signals. The linear range is approximately:

|Vid| < √2 · VOV (for ≤ 10% distortion)

Beyond this, one transistor steals all the tail current and the other shuts off.

📘 Input Pair Selection

NMOS pair: higher gm per unit current (faster), but higher 1/f noise. PMOS pair: lower 1/f noise, body effect eliminable, input CM range includes ground. Complementary: rail-to-rail input CM but gain varies across range.

7. Diff Pair with Active Load

Replacing resistor loads with a PMOS current mirror converts the differential signal to single-ended while doubling the gain.

VDD──────────VDD │ │ [M3]────────[M4] ← PMOS mirror load │ │ ├─ (int.) ├─ V_out │ │ [M1]────────[M2] ← NMOS diff pair └──────┬──────┘ [M5] ← tail current source │ GND
Av = gm1 × (ro2 ∥ ro4)

The mirror (M3-M4) folds the signal from the left branch into the right branch, creating a single-ended output. This is the first stage of the classic two-stage op-amp (five-transistor OTA).

🔴 Systematic Offset

The current mirror load introduces a half-circuit delay: the signal through M1→M3→M4 arrives at the output later than the direct path through M2. At high frequencies, this mismatch degrades CMRR and introduces systematic offset.

8. Common-Mode Rejection (CMRR)

CMRR = |Adm / Acm| = gm × 2RSS

The CMRR depends entirely on the tail current source impedance. A simple current mirror tail gives moderate CMRR; a cascode tail provides much higher rejection.

Tail Source TypeRSSTypical CMRR
ResistorR (fixed)20–40 dB
Simple mirrorro40–60 dB
Cascode mirrorgmro²80–100+ dB

9. Amplifier Comparison Summary

TopologyAvRinRoutBWBest For
Common-Source−gmRD∞RD∥roModerateGeneral amplification
CS + Degeneration−RD/RS∞RDWideLinear gain stages
Common-Gate+gmRD1/gmRD∥roWideWideband, cascode
Source Follower≈ 0.8–0.9∞1/gmVery WideBuffering, level shift
Telescopic Cascode(gmro)²/2∞gmro²HighHigh-gain OTA
Diff Pair + Mirrorgm(ro∥ro)∞ro∥roModerateOp-amp first stage

10. Numerical Examples

Example 1: CS Amplifier Gain

// NMOS CS with PMOS active load // I_D = 200μA, V_OV = 200mV, V_A,n = 10V, V_A,p = 15V g_m = 2I_D/V_OV = 2×200μ/0.2 = 2 mA/V r_o,n = V_A,n/I_D = 10/200μ = 50 kΩ r_o,p = V_A,p/I_D = 15/200μ = 75 kΩ A_v = −g_m × (r_o,n ∥ r_o,p) = −2m × (50k ∥ 75k) = −2m × 30k = −60 V/V (35.6 dB)

Example 2: Differential Pair CMRR

// I_SS = 400μA (200μA each side), V_OV = 200mV // Tail source: cascode mirror, V_A = 10V g_m = 2×200μ/0.2 = 2 mA/V r_o_tail = 10/400μ = 25 kΩ (basic) R_SS_cascode = g_m_tail × r_o² = 2m × (25k)² = 1.25 GΩ CMRR = g_m × 2R_SS = 2m × 2 × 1.25G = 5 × 10⁶ (134 dB)

Example 3: Telescopic Cascode Gain

// All transistors: g_m = 2 mA/V, r_o = 50 kΩ // Intrinsic gain per transistor: g_m × r_o = 2m × 50k = 100 V/V // NMOS cascode R_out: R_N = g_m × r_o × r_o = 100 × 50k = 5 MΩ // PMOS cascode R_out (same): R_P = 5 MΩ A_v = g_m1 × (R_N ∥ R_P) = 2m × 2.5M = 5000 V/V (74 dB) // ≈ (g_m r_o)² / 2 = 100² / 2 = 5000 ✓

🔁 Blog 3 Recap

  • CS amplifier: high gain, inverting, limited by Miller effect on Cgd.
  • CG amplifier: non-inverting, low Rin, wideband — ideal as cascode partner.
  • Source follower: near-unity gain buffer; body effect limits gain to ~0.85.
  • Cascode = CS + CG → gain ≈ (gmro)², with telescopic or folded variants.
  • The differential pair rejects common-mode; CMRR depends on tail source impedance.
  • Active mirror load converts differential to single-ended with doubled gain.

📚 Next up — Blog 4: Op-Amp & OTA Architectures — two-stage, folded-cascode, gain-boosted, and class-AB output stages.

↑ Back to Table of Contents
Labels:

Comments

Post a Comment

Popular posts from this blog

Module 1 — SystemVerilog Basics

By
VLSI Verification  •  SystemVerilog Series Module 1 — SystemVerilog Basics A complete, example-driven walkthrough of SystemVerilog fundamentals: data types, variables vs nets, arrays of every flavor, strings, enums, structs, unions, and typedef — the building blocks every verification engineer needs before UVM. 🧩 Beginner → Intermediate ⏱ ~25 min read 💻 Code Examples Included 📑 Table of Contents Introduction to SystemVerilog Verilog vs SystemVerilog Data Types: 2-State vs 4-State Logic Variables and Nets Arrays: Packed vs Unpacked Dynamic Arrays Queues Associative Arrays Strings Enumerations Structures Unions Typedef 1 Introduction to SystemVerilog SystemVerilog (IEEE 1800) is a unified hardware description and verification language (HDVL). It extends Verilog (IEEE 1364) with powerful constructs for design (interfaces, always_comb/always_ff, enhanced d...
Post a Comment
Read more

GPU Memory System & Interconnect: How Data Travels Inside a Modern GPU

By
GPU Memory System & Interconnect: How Data Travels Inside a Modern GPU Modern GPUs deliver incredible computing power by processing thousands of operations simultaneously. While compute cores often receive the spotlight, the real performance of a GPU depends heavily on how efficiently data moves between memory and compute units. A GPU memory system is designed to provide extremely high bandwidth while keeping latency as low as possible. This is achieved through a collection of specialized hardware components working together, including the Memory Controller, HBM/GDDR memory, Crossbar, Network-on-Chip (NoC), DMA Engine, PCIe Interface, and NVLink. In this article, we'll explore each component in detail and understand how they collectively enable high-performance parallel computing. Why Does GPU Memory Matter? Every GPU application—from gaming and graphics rendering to AI model training and scientific simulations—requires continuous movement of enormous amounts of data. For examp...
Post a Comment
Read more

Clock Domain Crossing (CDC): A Complete Beginner's Guide to Metastability, Synchronizers & Safe Data Transfer

By
Clock Domain Crossing (CDC): A Complete Beginner's Guide to Metastability, Synchronizers & Safe Data Transfer Modern System-on-Chip (SoC) designs rarely operate with a single clock. Instead, different modules such as CPUs, GPUs, memory controllers, communication interfaces, and peripherals often run at different clock frequencies or even use completely independent clock sources . When data moves from one clock domain to another, timing uncertainty can cause serious problems such as metastability , data corruption , and unpredictable system behaviour . This challenge is known as Clock Domain Crossing (CDC) . CDC is one of the most important topics in ASIC Design , RTL Design , ASIC Verification , FPGA Design , and SoC Architecture . Every modern chip—from smartphones to automotive processors—uses CDC techniques to ensure reliable communication between multiple clock domains. In this article, we'll explore CDC fundamentals, metastability, synchronization techniques, asynchro...
Post a Comment
Read more

AXI Verification Interview Questions and Real-World Debugging

By
AMBA Protocol Series · Part 10 of 10 AXI Verification Interview Questions and Real-World Debugging Common protocol violations, how to read them off a waveform, and a curated set of interview questions with concise, correct answers — the capstone of the core 10-day series. AMBA Protocol Series: From APB & AHB to AXI — A Complete Guide for VLSI Engineers This wraps up the core 10-day series. Everything here draws directly on Days 1–9 — if any answer below feels unfamiliar, that's a good signal for which earlier post to revisit. (If you want to go further, see the 20-day extended list at the end of this post.) In This Article Common Protocol Violations Debugging From a Waveform Interview Questions and Answers Series Recap Extending the Series 1. Common Protocol Violations VALID deasserted before handshake — a source drops VALID before READY ever went high (violates the Day 8 stabi...
Post a Comment
Read more

Cache Basics and Cache Mapping Techniques

By
  Cache Basics and Cache Mapping Techniques  Modern processors execute billions of instructions every second. However, processor speed has increased much faster than main memory (RAM) speed. This difference, known as the memory wall , creates a performance bottleneck because the CPU often has to wait for data from slower memory. To solve this problem, computer systems use cache memory —a small, high-speed memory located between the CPU and the main memory. In this article, we will understand the fundamentals of cache memory, the principle of locality, cache organization, and the three major cache mapping techniques. What is Cache Memory? Cache memory is a small, high-speed memory that stores copies of frequently accessed data from the main memory. Since accessing cache is much faster than accessing RAM, the CPU first checks whether the required data is available in the cache. If the data is found in the cache, it is called a cache hit . Otherwise, the CPU fetches the dat...
Post a Comment
Read more

Timing Basics in Static Timing Analysis (STA): Delay Models, Sequential Timing, and Wire Delays

By
Timing Basics in Static Timing Analysis (STA) Static Timing Analysis (STA) is one of the most important verification techniques used in modern VLSI design. Before a chip is manufactured, engineers must verify that every signal reaches its destination within the required clock period. Even if a design passes functional simulation, it may still fail after fabrication because of timing violations. Unlike simulation, Static Timing Analysis mathematically analyzes every timing path without applying input test vectors. This makes STA significantly faster and capable of analyzing millions of timing paths efficiently. Table of Contents What is Static Timing Analysis? Why STA is Required Propagation Delay Contamination Delay Cell Delay Models Combinational Gate Delay Sequential Timing Setup Time Hold Time Wire Delay RC Delay Model PVT Corners Worked Examples Interview Questions Key Takeaways What is Static Timing Analysis? Static Ti...
Post a Comment
Read more

Computer Architecture Interview Question Part 1

By
Skip to content Computer Architecture Interview Series Part 1 · CPU Basics · RISC vs CISC · ISA 50 Most Asked Computer Architecture Interview Questions (Part 1) The foundational round every VLSI, ASIC, and CPU design interview opens with: instruction set architecture, RISC vs CISC trade-offs, Von Neumann vs Harvard design, registers, endianness, and the fetch-decode-execute cycle — explained the way interviewers actually expect you to answer.  40 Questions (Q1–Q40) ⌛ 22 min read  VLSI & Computer Architecture Interviews On this page Foundations of Computer Architecture RISC vs CISC — Core Differences Von Neumann, Harvard & the Semantic Gap Architecture Styles, Endianness & Registers ILP, VLIW, Superscalar & Amdahl's Law Register Files, Microcontrollers & the Fetch Cycle Tip...
Post a Comment
Read more