ANALOG DESIGN BLOG 6 — NOISE, MATCHING & LAYOUT FOR ANALOG

Analog Design Series — Blog 6 of 7

Noise, Matching & Layout for Analog

Thermal noise, flicker noise, input-referred analysis, Pelgrom's law, common-centroid techniques, and layout practices that make or break analog silicon

📑 Table of Contents

1. Thermal Noise Fundamentals
2. Flicker (1/f) Noise
3. Noise in MOSFET Amplifiers — Input-Referred Noise
4. Noise Optimization Strategies
5. Pelgrom's Law & Transistor Matching
6. Mismatch in Differential Pairs & Current Mirrors
7. Common-Centroid & Interdigitated Layout
8. Guard Rings, Shielding & Substrate Noise
9. Analog Layout Parasitics & Best Practices
10. Numerical Examples — Noise & Matching Calculations

1. Thermal Noise Fundamentals

Thermal noise (Johnson-Nyquist noise) arises from random thermal agitation of charge carriers in any conductor. It exists in every resistor and every MOSFET channel regardless of applied bias, and sets the fundamental noise floor in analog circuits.

Resistor Thermal Noise

A resistor R at absolute temperature T generates an open-circuit noise voltage with a power spectral density (PSD):

S_v(f) = 4kTR    [V²/Hz]
v_n,rms = √(4kTR·Δf)    over bandwidth Δf

Equivalently, the short-circuit noise current PSD is Si = 4kT/R. Thermal noise is white — its PSD is flat across frequency — and has a Gaussian amplitude distribution.

MOSFET Channel Thermal Noise

The conducting channel of a MOSFET behaves like a distributed resistor. Its drain-current noise PSD is:

S_id = 4kTγg_m    [A²/Hz]

where γ is the excess noise factor: γ = 2/3 for long-channel devices, rising to 1–2 in deep-submicron technologies due to hot-electron effects and channel-length modulation.

🔖 Note — Noise Temperature

The noise factor γ is one of the most important process-dependent parameters. Foundry PDKs provide BSIM4 noise model coefficients (NOIA, NOIB, NOIC, EF, EM) that capture γ implicitly. Always simulate with foundry models rather than assuming γ = 2/3.

Gate-Induced Noise

At high frequencies, capacitive coupling between the noisy channel and the gate induces a gate noise current:

S_ig = 4kTδg_g    where g_g = ω²C_gs²/(5g_m),   δ ≈ 4/3

Gate-induced noise is correlated with drain noise (correlation coefficient c ≈ j·0.395) and becomes significant near f_T. For frequencies below f_T/5, it can usually be neglected.

💡 Design Insight

At room temperature (T = 300 K), the thermal voltage kT/q ≈ 26 mV and kT ≈ 4.14 × 10⁻²¹ J. A quick estimate: a 10 kΩ resistor has a noise density of √(4·4.14e-21·10e3) ≈ 12.9 nV/√Hz.

2. Flicker (1/f) Noise

Flicker noise dominates at low frequencies and has a power spectral density that rises inversely with frequency — hence "1/f noise." In MOSFETs, it arises from charge carriers being randomly trapped and de-trapped at the Si-SiO₂ interface.

MOSFET 1/f Noise Model

S_vg(f) = K / (C_ox² · W · L · f)    [V²/Hz]
(input-referred gate voltage noise)

where K is a process-dependent constant (typically 10⁻²⁵ to 10⁻²⁴ V²·F for NMOS; 2–5× lower for PMOS in most processes). The critical observations:

Factor	Effect on 1/f Noise	Design Implication
Gate area (W·L)	Svg ∝ 1/(WL)	Larger devices = less 1/f noise
Oxide capacitance	Svg ∝ 1/Cox²	Thinner oxide (newer nodes) helps
PMOS vs NMOS	Kp ≈ Kn/3 to Kn/5	PMOS input pairs for low-noise
Frequency	∝ 1/f	Dominates at low freq; use CDS/chopping

Flicker Noise Corner Frequency

The corner frequency f_c is where the 1/f PSD equals the thermal PSD:

f_c = K · g_m / (C_ox² · W · L · 4kTγ)

Typical values: f_c ranges from a few hundred Hz to tens of MHz depending on device size and process. A minimum-sized NMOS transistor can have f_c > 10 MHz; a large PMOS input transistor may push f_c below 1 kHz.

⚠️ Buried Channel vs. Surface Channel

Historically, PMOS devices were buried-channel, keeping carriers away from the noisy interface. In modern processes (below ~0.35 μm), PMOS is also surface-channel, narrowing the PMOS 1/f advantage. Always check your process's noise characterization data.

Techniques to Mitigate 1/f Noise

Chopper stabilization modulates the signal to a higher frequency (above f_c), amplifies it where only thermal noise exists, then demodulates back. Correlated double sampling (CDS) samples the noise and subtracts it on the next phase. Auto-zeroing stores the offset/noise on a capacitor and cancels it each clock cycle. All three trade noise bandwidth or clock feedthrough for reduced 1/f contribution.

3. Noise in MOSFET Amplifiers — Input-Referred Noise

To compare amplifiers fairly, we refer all noise sources to the input — modeling the amplifier as noiseless with an equivalent noise voltage source v_n and noise current source i_n at its input.

Single-Transistor CS Amplifier

For a common-source stage with drain resistor R_D (or active load M2):

v²_n,in = v²_n,M1 + v²_n,load/A²_v

For MOSFET active load:   v²_n,in = 4kTγ(1/g_m1 + g_m2/g²_m1)

The load transistor's noise is divided by the gain squared when referred to the input. This means the input transistor dominates — always optimize M1 for noise.

Differential Pair Input-Referred Noise

For a differential pair with active current-mirror load (M1/M2 input, M3/M4 load):

v²_n,in = 2 × [4kTγ/g_m1 + K_n/(C²_oxW₁L₁f)] × [1 + (g_m3/g_m1)(K_load/K_input)]

The factor of 2 accounts for both input transistors. The term (g_m3/g_m1) shows that the load pair's transconductance should be kept much smaller than the input pair's — or equivalently, the load devices should be biased at lower current density.

💡 Noise Optimization Rule of Thumb

For a 5-transistor OTA: make input-pair (g_m/I_D) as high as possible (weak or moderate inversion), and the load-pair (g_m/I_D) low (strong inversion). Also make the input pair PMOS if the process allows a K_p advantage.

Noise Bandwidth and Integrated Noise

Total integrated noise depends on the noise bandwidth, which for a first-order system with 3-dB frequency f_−3dB is:

NBW = (π/2) · f_−3dB    (noise bandwidth for first-order rolloff)

For a second-order Butterworth, NBW ≈ 1.11 · f_−3dB. The total rms input noise is then v_n,rms = √(S_vn · NBW) for the thermal component, plus the integrated 1/f contribution from f_min to f_max:

v²_n,1/f = (K / C²_oxWL) · ln(f_max/f_min)

4. Noise Optimization Strategies

g_m/I_D Methodology for Noise

The input-referred thermal noise voltage of a MOSFET is inversely proportional to g_m. Since g_m = (g_m/I_D) × I_D, the designer has two knobs: increase bias current, or increase g_m/I_D by biasing in weak/moderate inversion.

S_vg,thermal = 4kTγ/g_m = 4kTγ / [(g_m/I_D) · I_D]

In weak inversion (g_m/I_D ≈ 38 V⁻¹ at 300 K), you get maximum transconductance per unit current — ideal for ultra-low-power, noise-limited designs. The trade-off is reduced speed (f_T drops) and larger devices.

Device Sizing for 1/f Noise

Since 1/f noise scales as 1/(WL), simply increasing gate area reduces it. But increasing W raises C_gs (reducing speed), and increasing L reduces g_m (for constant V_OV). The optimal strategy:

🔖 Sizing Strategy

For bandwidth-limited designs: increase W (keeps g_m and speed) and accept larger capacitance. For ultra-low-noise, low-frequency designs: increase L (directly reduces 1/f noise) and compensate g_m loss by increasing W proportionally, keeping W/L constant and the bias point unchanged.

Power-Noise Trade-off

The fundamental trade-off is captured by the noise efficiency factor (NEF):

NEF = v_n,rms · √(2·I_total / (π·V_T·4kT·BW))

NEF = 1 is the theoretical minimum (a single BJT). Practical CMOS amplifiers achieve NEF = 2–5. State-of-the-art chopper-stabilized amplifiers reach NEF ≈ 1.0–1.5 by exploiting noise-bandwidth reduction.

Choosing PMOS vs. NMOS Input Pair

Factor	NMOS Input	PMOS Input
Thermal noise	Lower (higher gm/W)	Slightly higher
1/f noise	Higher Kn	Lower Kp (2–5× advantage)
Speed (fT)	Faster (higher μn)	Slower
Best application	Wideband, high-freq	Low-freq, precision, sensor

5. Pelgrom's Law & Transistor Matching

No two transistors on a chip are identical. Random dopant fluctuation, oxide thickness variation, and line-edge roughness cause mismatch — the random difference between nominally identical devices placed close together.

Pelgrom's Law

Marcel Pelgrom (1989) showed that the standard deviation of any device parameter P between two matched transistors follows:

σ(ΔP) = A_P / √(W·L)

where A_P is a process-dependent matching coefficient. The two most critical parameters:

σ(ΔV_th) = A_VT / √(W·L)    [mV]
σ(Δβ/β) = A_β / √(W·L)    [%]

Process Node	AVT (NMOS) [mV·μm]	AVT (PMOS) [mV·μm]	Aβ [%·μm]
180 nm	4–6	5–8	1–2
65 nm	3–4.5	4–6	1–1.5
28 nm	1.5–3	2–4	0.8–1.2
7 nm (FinFET)	0.8–1.5	1–2	0.5–0.8

💡 Rule of Thumb

To halve the mismatch σ(ΔV_th), you must quadruple the gate area (W×L). This is why precision analog blocks consume significant silicon area.

Beyond Pelgrom: Proximity & Systematic Mismatch

Pelgrom's law describes random mismatch for adjacent devices. Additional systematic mismatch comes from gradients (thermal, stress, doping), device orientation, proximity to other structures, and distance. These require layout techniques (see Sections 7–9) to control.

6. Mismatch in Differential Pairs & Current Mirrors

Differential Pair Offset Voltage

The input-referred offset voltage of a differential pair has two components:

σ(V_os) = √[σ²(ΔV_th) + (V_OV/2)² · σ²(Δβ/β)]

where V_OV = V_GS − V_th is the overdrive voltage. The V_th mismatch term dominates in weak and moderate inversion (small V_OV). The β mismatch term grows with overdrive. For minimum offset:

🔖 Offset Minimization

Use low V_OV (moderate inversion, V_OV ≈ 50–100 mV) to suppress the β mismatch contribution. Use large W·L to suppress both terms via Pelgrom's law. Use common-centroid layout to cancel gradients.

Current Mirror Mismatch

For a simple current mirror, the output current error is:

σ(ΔI/I) = √[σ²(Δβ/β) + (2/V_OV)² · σ²(ΔV_th)]

Note the 2/V_OV factor: at V_OV = 100 mV, a 1 mV V_th mismatch causes 2% current error. This is why precision mirrors use either large overdrive or cascode structures (which don't improve matching per se, but improve output resistance and PSRR).

Monte Carlo Simulation

Foundry PDKs provide statistical models for Monte Carlo mismatch analysis. Run at least 200–500 iterations for 3σ confidence. Track key metrics: offset voltage, CMRR, PSRR, gain error, current mirror accuracy. Always run both process corners (global variation) and mismatch (local variation) — they stress different failure modes.

🔴 Common Mistake

Running only corner simulations (SS, FF, SF, FS) captures global variation but misses random mismatch entirely. A circuit can pass all corners yet fail in silicon due to local V_th mismatch. Always include Monte Carlo mismatch runs.

7. Common-Centroid & Interdigitated Layout

Systematic mismatch from die-level gradients (thermal, stress, oxide thickness) can dwarf random mismatch. Layout techniques exist to make matched devices see the same average gradient.

Common-Centroid Principle

Two matched elements A and B are arranged so their geometric centroids coincide. For any linear gradient across the die, both elements experience the same average parameter value, and the gradient-induced mismatch cancels exactly.

Patterns for Transistor Pairs

Pattern	Arrangement	Cancels	Use Case
ABBA	A B B A (1-D)	Linear gradient in one axis	Differential pair, basic mirror
ABBA-BAAB	Two rows: ABBA / BAAB	Gradients in both X and Y	High-precision diff pair
Interdigitated	A B A B A B …	Linear gradient, partially	Resistor arrays, capacitor arrays
2-D common-centroid	Checkerboard ABBABAAB	X, Y, and diagonal gradients	DAC unit elements, precision mirrors

💡 ABBA Layout for Diff Pair

Split each input transistor into two fingers: M1a, M1b, M2a, M2b. Place them as M1a–M2a–M2b–M1b (ABBA). Both M1 and M2 now have the same centroid, canceling any linear V_th gradient. Add dummy fingers at each end for etch uniformity.

Rules for Effective Common-Centroid Layout

1. Identical orientation: All matched devices must have the same channel direction (gate poly runs the same way) to see the same stress and implant angle effects. 2. Minimum spacing: Keep matched devices as close as possible — mismatch increases with distance (σ² adds a D²-dependent term beyond Pelgrom). 3. Same well, same environment: Place matched devices in the same well region, surrounded by identical structures. 4. Symmetric routing: Interconnect parasitics must be symmetric — a beautifully matched transistor pair is ruined by asymmetric drain wiring.

Capacitor and Resistor Matching

For matched capacitor arrays (e.g., in a SAR ADC): use unit-element design, common-centroid arrangement, identical perimeter-to-area ratios, and dummy capacitors on all edges. Capacitor matching follows its own Pelgrom-like relation: σ(ΔC/C) = A_C/√(Area).

8. Guard Rings, Shielding & Substrate Noise

Substrate Noise — The Analog Killer

In mixed-signal SoCs, digital switching injects current spikes into the shared substrate. These substrate noise currents modulate analog transistor thresholds and back-gate bias, appearing as supply noise and offset drift.

Guard Rings

A guard ring is a ring of diffusion (or well tap) surrounding a sensitive device, tied to a clean supply. It serves two purposes:

N+ guard ring in P-substrate: collects minority-carrier electrons injected by NMOS switching. P+ guard ring around N-well: provides a low-impedance path for substrate currents, preventing them from reaching the analog device's back gate.

🔖 Guard Ring Effectiveness

A single guard ring typically provides 20–40 dB of substrate noise attenuation. Double guard rings (nested N+ and P+ rings with separate supply connections) can achieve 40–60 dB. The ring must be continuous (no gaps) and connected to a dedicated quiet supply pad — not shared with digital VDD.

Deep N-Well Isolation

Many modern processes offer a deep N-well (DNW) layer that forms a reverse-biased junction isolating the P-substrate from the P-well containing analog NMOS devices. DNW isolation can provide 40+ dB additional rejection, especially at frequencies above 100 MHz where guard rings lose effectiveness.

Supply & Signal Shielding

Separate analog/digital supplies: Dedicate AVDD/AVSS pads physically separated from DVDD/DVSS on the die and package. Star-point grounding at the pad ring minimizes shared-impedance coupling.

Metal shielding: Run a grounded metal plane (connected to AVSS) between sensitive analog traces and noisy digital buses. On-chip coupling follows 1/d² between parallel traces; shielding with a grounded plane between them improves isolation by 20–30 dB.

⚠️ Shield Grounding

A floating metal shield is worse than no shield — it capacitively couples to both aggressor and victim without providing a low-impedance return path. Always ground shields to a quiet supply.

Differential Routing for Noise Rejection

Route differential signal pairs (e.g., op-amp inputs, ADC reference lines) as closely spaced parallel traces on the same metal layer. Any common-mode substrate or supply noise couples equally to both lines and is rejected by the CMRR of the downstream differential stage.

9. Analog Layout Parasitics & Best Practices

Critical Parasitic Elements

Parasitic	Source	Impact	Mitigation
Junction capacitance (Cdb, Csb)	Source/drain to bulk PN junction	Reduces bandwidth, adds noise	Minimize diffusion area, use shared S/D
Interconnect capacitance	Metal-to-metal, metal-to-substrate	Loads high-impedance nodes	Short wires on high-Z nodes, shielding
Interconnect resistance	Thin/narrow metal	IR drop, thermal noise, RC delay	Wide metals for bias/supply, upper layers
Via resistance	Stacked vias	Adds noise, voltage drop	Multiple via arrays, via redundancy
Poly gate resistance	Long poly fingers	Adds thermal noise, degrades fmax	Gate contacts on both ends, fingered layout
Well resistance	Sparse well taps	Substrate bounce, latch-up risk	Frequent well/substrate taps

High-Impedance Node Protection

Nodes like the gate of a cascode device, a sample-and-hold capacitor top plate, or a comparator input carry signal on very high impedance. Even femtofarads of parasitic capacitance or picoamps of leakage degrade performance. Rules:

1. Keep metal traces short — go directly from device to device with minimum routing. 2. Surround with a grounded shield (but ensure it doesn't add excessive capacitance). 3. Avoid crossing digital bus lines over high-Z nodes. 4. Use upper metal layers (farther from substrate) for high-Z routing.

Electromigration & Current Density

DC current density limits (process-specific, typically 1–2 mA/μm for lower metals) must be respected on all bias and supply lines. Even though analog currents are often small, mirror reference lines that fan out to many copies can carry surprisingly high total current.

💡 Layout Review Checklist

DRC (design rule check) catches spacing/width violations. LVS (layout vs. schematic) verifies connectivity. But neither checks analog quality — you need manual review for: matching (common-centroid?), guard rings, high-Z node exposure, supply routing width, and parasitic-sensitive connections. Post-layout extraction with RC parasitic back-annotation is essential; compare extracted simulation results against schematic simulation.

Best-Practice Summary

Orientation: All matched transistors same direction. Symmetry: Layout mirrors the schematic's symmetry axis. Dummy structures: Dummy poly fingers on edges, dummy capacitors on array borders. Well ties: Every 10–20 μm of well width. Guard rings: Around every sensitive analog block. Extracted simulation: Mandatory before tapeout.

10. Numerical Examples — Noise & Matching Calculations

Example 1: Input-Referred Noise of a CS Amplifier

🔖 Problem

A common-source NMOS amplifier has g_m1 = 2 mA/V and an active PMOS load with g_m2 = 0.5 mA/V. The process parameters are K_n = 5 × 10⁻²⁵ V²·F, K_p = 1.2 × 10⁻²⁵ V²·F, and C_ox = 8.6 fF/μm². Input transistor: W₁/L₁ = 20 μm / 0.5 μm. Load transistor: W₂/L₂ = 10 μm / 0.5 μm. γ = 1 for both. Find the input-referred thermal and 1/f noise PSDs at 10 kHz.

Step 1 — Thermal noise (white):

S_vn,thermal = 4kTγ · (1/g_m1 + g_m2/g²_m1)
= 4 × 4.14×10⁻²¹ × 1 × (1/2×10⁻³ + 0.5×10⁻³ / 4×10⁻⁶)
= 1.656×10⁻²⁰ × (500 + 125)
= 1.656×10⁻²⁰ × 625 = 1.035 × 10⁻¹⁷ V²/Hz
⇒ √S_vn ≈ 3.22 nV/√Hz

Step 2 — 1/f noise at 10 kHz:

S_vn,1/f = [K_n/(C²_ox·W₁·L₁) + K_p·g²_m2/(C²_ox·W₂·L₂·g²_m1)] / f

C²_ox = (8.6×10⁻¹⁵ × 10¹²)² = (8.6×10⁻³)² = 7.396×10⁻⁵ F²/m⁴
Term 1: 5×10⁻²⁵ / (7.396×10⁻⁵ × 10×10⁻¹²) = 5×10⁻²⁵ / 7.396×10⁻¹⁶ = 6.76×10⁻¹⁰ V²
Term 2: 1.2×10⁻²⁵ × (0.0625) / (7.396×10⁻⁵ × 5×10⁻¹²) = 7.5×10⁻²⁷ / 3.698×10⁻¹⁶ = 2.03×10⁻¹¹ V²

S_vn,1/f(10 kHz) = (6.76×10⁻¹⁰ + 2.03×10⁻¹¹) / 10⁴ = 6.96 × 10⁻¹⁴ V²/Hz
⇒ √S_vn ≈ 264 nV/√Hz at 10 kHz

💡 Key Takeaway

At 10 kHz, the 1/f noise (264 nV/√Hz) completely dominates the thermal noise (3.2 nV/√Hz). The corner frequency for this design is very high. To bring f_c below 10 kHz, the input device area W₁·L₁ would need to increase by roughly 80×, or the designer should switch to a PMOS input pair.

Example 2: Differential Pair Offset from Pelgrom's Law

🔖 Problem

A differential pair uses NMOS input transistors with W/L = 50 μm / 1 μm in a 65 nm process (A_VT = 4 mV·μm, A_β = 1.5%·μm). The overdrive voltage V_OV = 100 mV. Find the 1σ and 3σ input offset voltage.

Step 1 — Individual mismatch terms:

σ(ΔV_th) = A_VT / √(W·L) = 4 / √(50 × 1) = 4/7.07 = 0.566 mV
σ(Δβ/β) = A_β / √(W·L) = 1.5 / √50 = 0.212 %

Step 2 — Combined offset voltage:

σ(V_os) = √[σ²(ΔV_th) + (V_OV/2)² · σ²(Δβ/β)]
= √[(0.566)² + (50)² × (0.00212)²]   [mV]
= √[0.320 + 0.01124]
= √0.3313 = 0.576 mV (1σ)

Step 3 — 3σ offset:

3σ(V_os) = 3 × 0.576 = 1.73 mV

The V_th mismatch dominates (0.566 mV vs. 0.106 mV from β). With V_OV = 100 mV, increasing the overdrive won't help much — larger gate area is the only way to reduce offset further.

Example 3: Current Mirror Matching

🔖 Problem

A simple 1:1 PMOS current mirror uses W/L = 10 μm / 2 μm devices in 180 nm CMOS (A_VT = 6 mV·μm, A_β = 1.8%·μm). The mirror operates at I_REF = 50 μA with V_OV = 150 mV. Find the 3σ current mismatch.

σ(ΔV_th) = 6 / √(10×2) = 6/4.47 = 1.342 mV
σ(Δβ/β) = 1.8 / √20 = 0.402 %

σ(ΔI/I) = √[σ²(Δβ/β) + (2·σ(ΔV_th)/V_OV)²]
= √[(0.00402)² + (2×0.001342/0.15)²]
= √[(1.616×10⁻⁵) + (0.01789)²]
= √[1.616×10⁻⁵ + 3.2×10⁻⁴]]
= √(3.362×10⁻⁴) = 1.83 % (1σ)

3σ(ΔI/I) = 3 × 1.83% = 5.5 %
3σ(ΔI) = 0.055 × 50 μA = 2.75 μA

⚠️ Practical Interpretation

A 5.5% (3σ) current error may be acceptable for coarse biasing but is far too large for precision circuits like DAC current cells or bandgap references. To achieve <0.5% (3σ), the gate area must increase by roughly (5.5/0.5)² ≈ 120× — e.g., W/L = 50 μm / 10 μm or equivalent unit-element arrays with common-centroid layout.

🔁 Blog 6 Recap — Noise, Matching & Layout

• Thermal noise is white (4kTγg_m) and sets the broadband floor; 1/f noise dominates at low frequencies and scales as 1/(WL)
• Input-referred noise lets us compare amplifiers fairly — optimize the input transistor first (it dominates)
• PMOS input pairs offer 2–5× lower 1/f noise; weak inversion biasing maximizes g_m/I_D
• Pelgrom's law: σ(ΔP) = A_P/√(WL) — halving mismatch requires 4× area
• V_th mismatch dominates diff pair offset at low overdrive; β mismatch matters at high V_OV
• Common-centroid layout (ABBA) cancels linear gradients; 2-D patterns cancel X+Y gradients
• Guard rings & deep N-well provide 20–60 dB substrate noise isolation
• Post-layout extraction with parasitic back-annotation is mandatory for every analog tapeout

🔜 Next Up — Blog 7: PLLs, Data Converters & Mixed-Signal Integration

Phase-locked loops, charge pumps, VCO design, ADC/DAC architectures, bandgap references, LDOs, and mixed-signal layout

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