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Part 1 · CPU Basics · RISC vs CISC · ISA
50 Most Asked Computer Architecture Interview Questions (Part 1)
The foundational round every VLSI, ASIC, and CPU design interview opens with: instruction set architecture, RISC vs CISC trade-offs, Von Neumann vs Harvard design, registers, endianness, and the fetch-decode-execute cycle — explained the way interviewers actually expect you to answer.
Table of Contents
- Foundations of Computer Architecture
- RISC vs CISC — Core Differences
- Von Neumann, Harvard & the Semantic Gap
- Architecture Styles, Endianness & Registers
- ILP, VLIW, Superscalar & Amdahl's Law
- Register Files, Microcontrollers & the Fetch Cycle
- Tips for Freshers & Experienced
- Common Mistakes
- FAQ
- Related Articles
Intro Why This Guide
If you're preparing for a computer architecture interview — whether it's a campus placement, a VLSI design role, or an ASIC verification position — the first round almost always circles back to the same fundamentals: what is an instruction set architecture, how does RISC differ from CISC, and why does a processor's control unit matter. These aren't trivia questions. Interviewers use them to check whether you actually understand how a processor is built, not just whether you memorized definitions.
This is Part 1 of a five-part interview preparation series covering computer architecture end to end. Here we walk through the first 40 questions — everything from the definition of computer architecture itself to RISC vs CISC trade-offs, Von Neumann and Harvard memory models, endianness, register organization, instruction-level parallelism, and the fetch-decode-execute cycle. Each answer is written the way you'd want to explain it out loud in an interview: precise, structured, and backed by a concrete example wherever it helps.
Whether you're a fresher walking into your first technical round or an experienced engineer brushing up before a senior RTL or verification interview, these questions form the baseline every later round — pipelining, hazards, branch prediction, performance metrics — builds on. Bookmark this page and work through it section by section.
Context Why These Questions Are Asked in Interviews
Interviewers open with ISA and RISC vs CISC questions because they reveal whether a candidate understands the boundary between hardware and software — a distinction that matters directly in RTL design, verification, and physical design roles.
These questions are also a filter: someone who can clearly explain why RISC-V uses fixed-length encoding, or why x86 still dominates despite being CISC, demonstrates the kind of first-principles thinking that's hard to fake. It sets the tone for every architecture round that follows.
How to use this list
Use the search box below to jump to a specific question, or expand every answer at once to read through the whole section. Tap any question to reveal its full answer.
40 questions
Q1–Q2 Foundations of Computer Architecture
Q1 What is Computer Architecture? ▸
Computer Architecture refers to the design and organization of a computer system's fundamental operational structure. It defines how hardware components interact, how instructions are executed, and how data flows through the system. It encompasses the instruction set architecture (ISA), microarchitecture, and system-level design. Computer architecture bridges the gap between hardware engineering and software development, determining a machine's capabilities, performance characteristics, and power consumption.
Q2 What is an Instruction Set Architecture (ISA)? ▸
An Instruction Set Architecture (ISA) is the abstract interface between the hardware and the lowest-level software. It defines the set of instructions a processor can execute, data types, registers, addressing modes, memory architecture, interrupt handling, and I/O mechanisms. The ISA serves as a contract: any software written to that ISA will run on any processor implementing it. Examples include x86, ARM, MIPS, and RISC-V. The ISA is distinct from the microarchitecture, which is the specific hardware implementation of the ISA.
Q3–Q13 RISC vs CISC — Core Differences
Q3 What does RISC stand for and what are its key principles? ▸
RISC stands for Reduced Instruction Set Computer. Its key principles are: (1) A small, fixed-size instruction set where each instruction performs one simple operation. (2) Load-store architecture --- only load and store instructions access memory; all other operations use registers. (3) Fixed-length instruction encoding for simplified decoding. (4) Large register files to minimize memory access. (5) Hardwired control unit for faster execution. (6) Instructions typically execute in one clock cycle. (7) Emphasis on compiler optimization to arrange instructions efficiently. Examples include ARM, MIPS, RISC-V, and SPARC.
Q4 What does CISC stand for and what are its key principles? ▸
CISC stands for Complex Instruction Set Computer. Its key principles are: (1) A large set of instructions, many of which perform multi-step operations. (2) Instructions can directly access memory in arithmetic/logic operations (register-memory and memory-memory operations). (3) Variable-length instruction encoding. (4) Fewer general-purpose registers compared to RISC. (5) Microprogrammed control unit. (6) Single instructions can replace multiple RISC instructions. (7) Emphasis on hardware complexity to support powerful instructions. The primary example is the x86/x86-64 architecture used in Intel and AMD processors.
Q5 Compare RISC and CISC architectures in terms of instruction complexity. ▸
RISC instructions are simple, single-operation, and typically execute in one clock cycle. Each instruction performs one atomic task (e.g., ADD R1, R2, R3 adds two registers). CISC instructions are complex and can perform multi-step operations in a single instruction (e.g., ADD [memory], R1 fetches from memory, adds, and stores back). RISC requires more instructions to accomplish the same task but each runs faster. CISC requires fewer instructions but each takes multiple clock cycles. Modern CISC processors (like x86) internally decompose complex instructions into RISC-like micro-operations, blurring this distinction.
Q6 Why do RISC processors have large register files? ▸
RISC processors have large register files for several reasons: (1) The load-store architecture means all computation happens on registers, so more registers reduce the frequency of memory accesses. (2) Procedure calls can use register windows (as in SPARC) to avoid saving/restoring registers to the stack. (3) More registers allow compilers greater flexibility in register allocation, keeping more variables in fast register storage. (4) Reduced memory traffic improves performance since register access is 10-100x faster than cache access. Typical RISC processors have 32 general-purpose registers, compared to 8-16 in traditional CISC designs.
Q7 What is a load-store architecture? ▸
A load-store architecture is a design where only dedicated load and store instructions can access main memory. All arithmetic and logic operations operate exclusively on data held in registers. For example, to add a value from memory to a register, you must first LOAD the value into a register, then ADD the two registers. This simplifies the processor design because the execution unit doesn't need to handle memory addressing. It also makes pipelining more efficient since memory access stages are predictable. RISC architectures like ARM, MIPS, and RISC-V all use load-store architecture.
Q8 What is a register-memory architecture? ▸
A register-memory architecture allows arithmetic and logic instructions to have one operand in memory and one in a register. For example, ADD R1, [memory_address] adds the value at a memory location directly to R1 without a separate load instruction. Some CISC architectures even allow memory-memory operations where both operands are in memory. This reduces instruction count but complicates the pipeline since the execution unit must also handle memory address calculation and data fetching. The x86 architecture is a classic example of a register-memory architecture.
Q9 What is a hardwired control unit and how does it differ from microprogrammed control? ▸
A hardwired control unit generates control signals through fixed combinational logic circuits (gates, decoders, multiplexers). It is faster because signals propagate through hardware directly, but it is inflexible and difficult to modify. RISC processors prefer hardwired control because their simple, uniform instructions map well to fixed logic. A microprogrammed control unit stores control signals as microinstructions in a control memory (control store). Each machine instruction triggers a sequence of microinstructions. This is more flexible and easier to design for complex instructions but introduces the overhead of reading the control store. CISC processors traditionally used microprogrammed control.
Q10 Why do modern x86 processors translate CISC instructions into micro-ops? ▸
Modern x86 processors translate complex CISC instructions into simpler RISC-like micro-operations (μops) because: (1) Simple, uniform micro-ops can be efficiently pipelined, out-of-order executed, and superscalar dispatched. (2) The backend can be designed as a high-performance RISC engine while maintaining backward compatibility with the vast x86 software ecosystem. (3) Micro-ops enable advanced optimizations like micro-op fusion (combining related μops), macro-op fusion (combining sequential instructions), and micro-op caching. (4) Register renaming and speculative execution work more efficiently with uniform micro-ops. This approach, used since the Intel P6 microarchitecture (Pentium Pro, 1995), gives the best of both worlds.
Q11 What is the significance of fixed-length vs. variable-length instruction encoding? ▸
Fixed-length encoding (used by RISC) means every instruction occupies the same number of bits (e.g., 32 bits in MIPS/ARM). Advantages: instruction fetch is simple (always fetch N bytes), the next instruction address is trivially computed, and parallel decoding of multiple instructions is straightforward. Disadvantage: code density can be lower since simple instructions waste bits. Variable-length encoding (used by CISC like x86, where instructions range from 1 to 15 bytes) provides better code density since simple instructions use fewer bytes. However, it complicates instruction fetch and decode because the processor cannot determine instruction boundaries without partially decoding each instruction, making superscalar decode more complex and power-hungry.
Q12 What is the RISC-V architecture and why is it significant? ▸
RISC-V is an open-source instruction set architecture developed at UC Berkeley starting in 2010. Its significance lies in: (1) Open standard --- no licensing fees, unlike ARM, enabling anyone to design processors. (2) Modular design with a base integer ISA (RV32I/RV64I) and optional standard extensions (M for multiply, A for atomics, F/D for floating point, C for compressed instructions, V for vectors). (3) Clean, modern design unencumbered by legacy compatibility. (4) Growing ecosystem in academia, embedded systems, and increasingly in data centers and AI accelerators. (5) It promotes innovation and competition in processor design.
Q13 What is Thumb/Thumb-2 instruction encoding in ARM? ▸
Thumb is a compressed instruction set extension for ARM processors that uses 16-bit instructions instead of the standard 32-bit ARM instructions. It improves code density by approximately 30% at a slight performance cost. Thumb-2, introduced in ARMv6T2, extends Thumb by adding a mix of 16-bit and 32-bit instructions, achieving near-ARM performance with Thumb-like code density. The processor can switch between ARM and Thumb modes. Modern ARM Cortex-A processors use the AArch64 (ARMv8) 64-bit instruction set, which has a fixed 32-bit encoding, and AArch32 mode supports Thumb-2 for backward compatibility.
Q14–Q20 Von Neumann, Harvard & the Semantic Gap
Q14 What is the Von Neumann architecture? ▸
The Von Neumann architecture, proposed by John von Neumann in 1945, stores both instructions and data in the same memory and uses a single bus for both. Key characteristics: (1) A single memory space holds both program and data. (2) Instructions and data share the same bus (Von Neumann bottleneck). (3) The CPU fetches instructions and data sequentially from the same memory. (4) A program counter tracks the current instruction address. This simplifies design but creates a bandwidth bottleneck since instruction fetch and data access cannot happen simultaneously. Most modern systems use a modified Von Neumann architecture with separate L1 instruction and data caches to mitigate this bottleneck.
Q15 What is the Harvard architecture? ▸
The Harvard architecture uses physically separate memory and buses for instructions and data. Key characteristics: (1) Separate storage for instructions and data. (2) Separate buses allow simultaneous instruction fetch and data access. (3) Eliminates the Von Neumann bottleneck, increasing throughput. (4) Instructions and data can have different bit widths. Originally used in the Harvard Mark I computer (1944). Today, a Modified Harvard Architecture is common: separate L1 caches for instructions and data (Harvard-style) backed by a unified L2/L3 cache and main memory (Von Neumann-style). DSP processors and microcontrollers (like AVR, PIC) often use a pure Harvard architecture.
Q16 What is the Von Neumann bottleneck and how is it mitigated? ▸
The Von Neumann bottleneck occurs because instructions and data share the same memory bus, so the CPU cannot fetch an instruction and read/write data simultaneously. This limits throughput since the bus becomes a bandwidth constraint. Mitigation strategies include: (1) Cache hierarchy --- separate L1 instruction and data caches allow parallel access (Modified Harvard). (2) Wider memory buses and higher memory bandwidth (DDR, HBM). (3) Prefetching --- hardware or software anticipates future memory accesses. (4) Out-of-order execution --- the CPU reorders instructions to hide memory latency. (5) Multi-level cache hierarchy (L1/L2/L3) to keep frequently accessed data close to the CPU.
Q17 What is the difference between microarchitecture and ISA? ▸
The ISA is the abstract specification --- it defines what instructions exist, their binary encoding, register names, memory model, and programmer-visible behavior. It is the contract between hardware and software. The microarchitecture is the specific hardware implementation of an ISA --- it defines how the processor physically executes those instructions. Multiple microarchitectures can implement the same ISA differently. For example, Intel's Skylake, Ice Lake, and Alder Lake are different microarchitectures that all implement the x86-64 ISA. ARM's Cortex-A53 and Cortex-A78 are different microarchitectures implementing the ARMv8-A ISA. The ISA provides compatibility; the microarchitecture determines performance.
Q18 What are the advantages of RISC over CISC? ▸
Advantages of RISC: (1) Simpler hardware design leads to smaller die area and lower power consumption. (2) Fixed-length instructions simplify and speed up instruction decode. (3) Single-cycle execution of most instructions enables efficient pipelining. (4) Large register files reduce memory traffic. (5) Hardwired control is faster than microprogrammed. (6) Easier to design, verify, and achieve higher clock frequencies. (7) Better suited for compiler optimization. (8) Lower power consumption makes RISC dominant in mobile and embedded (ARM in smartphones, IoT). (9) Shorter design cycle and time-to-market.
Q19 What are the advantages of CISC over RISC? ▸
Advantages of CISC: (1) Higher code density --- fewer instructions per program reduces memory footprint and instruction cache pressure. (2) Backward compatibility --- the x86 ISA supports decades of legacy software. (3) Complex instructions can be faster when implemented efficiently in hardware (e.g., string operations, REP MOVSB). (4) Fewer instruction fetches reduce front-end bandwidth requirements. (5) Semantic gap between high-level languages and machine code is smaller, potentially simplifying compilation. (6) The massive x86 ecosystem (tools, libraries, optimized software) is a significant practical advantage.
Q20 What is the semantic gap in computer architecture? ▸
The semantic gap refers to the difference between high-level programming language constructs and the machine instructions available to implement them. A large semantic gap means many low-level instructions are needed to express a high-level operation. CISC aimed to close this gap by providing complex instructions that map closely to high-level constructs (e.g., LOOP, ENTER/LEAVE for procedure frames in x86). RISC philosophy argues that compilers can efficiently bridge the gap using simple instructions, and that complex instructions are rarely used by compilers anyway. Research showed that compilers used only a small subset of CISC instructions, supporting the RISC approach.
Q21–Q26 Architecture Styles, Endianness & Registers
Q21 What is an accumulator-based architecture? ▸
An accumulator-based architecture uses a single special register called the accumulator as the implicit destination (and often one source) for all arithmetic/logic operations. Instructions have the form: ADD X, which means Accumulator = Accumulator + Memory[X]. Advantages: short instruction encoding since one operand is implicit. Disadvantages: heavy memory traffic since intermediate results must be stored to and loaded from memory frequently when the accumulator is needed for another computation. Early computers like the EDVAC and many early microprocessors (Intel 8080, 6502) used accumulator architectures. Modern architectures have moved to general-purpose register designs.
Q22 What is a stack-based architecture? ▸
A stack-based architecture uses an implicit stack for operands. Instructions push operands onto the stack and operations pop operands, compute, and push results. For example, to compute A+B: PUSH A, PUSH B, ADD (pops two values, pushes their sum). Advantages: very compact instruction encoding (zero-address instructions), simple compiler code generation using reverse Polish notation. Disadvantages: the stack creates a bottleneck, re-accessing values deep in the stack is inefficient, and it does not map well to pipelined hardware. The Java Virtual Machine (JVM) and some HP calculators use a stack-based architecture. The Burroughs B5000 was a notable hardware stack machine.
Q23 What is the difference between big-endian and little-endian byte ordering? ▸
Endianness refers to the order in which bytes of a multi-byte data type are stored in memory. Big-endian stores the most significant byte at the lowest memory address (e.g., 0x12345678 is stored as 12 34 56 78). Little-endian stores the least significant byte first (stored as 78 56 34 12). x86 uses little-endian; many networking protocols use big-endian (network byte order). ARM and RISC-V are bi-endian (configurable). Endianness matters for data serialization, network communication, file formats, and cross-platform compatibility. Mismatched endianness causes data corruption if not handled.
Q24 What are general-purpose registers (GPRs)? ▸
General-purpose registers are CPU registers that can be used for a variety of purposes including storing operands, addresses, and intermediate computation results. Unlike special-purpose registers (like the program counter or status register), GPRs are not dedicated to a specific function by the hardware. MIPS has 32 GPRs ($0-$31), ARM AArch64 has 31 GPRs (X0-X30), x86-64 has 16 GPRs (RAX-R15). More GPRs allow compilers to keep more variables in registers, reducing memory accesses. However, more registers mean more bits needed in instruction encoding to specify register operands and more state to save during context switches.
Q25 What is register windowing as used in SPARC? ▸
Register windowing, used in the SPARC architecture, provides overlapping sets of registers to reduce the overhead of procedure calls. Instead of saving/restoring registers on the stack during function calls, the processor shifts to a new window of registers. Each window has three sections: input, local, and output registers. The output registers of the caller overlap with the input registers of the callee, enabling zero-copy parameter passing. When all windows are used, a window overflow trap saves the oldest window to memory. This mechanism speeds up function calls significantly in deeply nested code but adds hardware complexity and increases context switch time.
Q26 What is the role of a compiler in RISC architecture? ▸
In RISC architecture, the compiler plays a critical role because the hardware is deliberately simple. The compiler is responsible for: (1) Instruction scheduling --- reordering instructions to avoid pipeline stalls and hazards. (2) Register allocation --- efficiently mapping variables to the large register file to minimize memory accesses. (3) Loop optimization --- unrolling, software pipelining, and vectorization. (4) Delayed branch filling --- inserting useful instructions in branch delay slots. (5) Strength reduction and peephole optimization. (6) Generating efficient instruction sequences for complex operations that would be single instructions in CISC. The RISC philosophy shifts complexity from hardware to the compiler.
Q27–Q35 ILP, VLIW, Superscalar & Amdahl's Law
Q27 What is instruction-level parallelism (ILP)? ▸
Instruction-level parallelism (ILP) refers to the degree to which instructions in a program can be executed simultaneously. ILP exists when instructions are independent --- they don't depend on each other's results and don't conflict for resources. Techniques to exploit ILP include: (1) Pipelining --- overlapping execution of sequential instructions. (2) Superscalar execution --- issuing multiple instructions per cycle to parallel functional units. (3) Out-of-order execution --- dynamically reordering instructions to fill idle slots. (4) VLIW/EPIC --- compiler explicitly packages independent instructions. (5) Speculative execution --- executing instructions before knowing if they are needed. The practical ILP in typical programs is limited (typically 2-4 IPC) due to dependencies and branches.
Q28 What is VLIW architecture? ▸
Very Long Instruction Word (VLIW) architecture packs multiple independent operations into a single long instruction word. The compiler, not the hardware, is responsible for finding parallelism and scheduling operations into VLIW bundles. For example, a 128-bit instruction might contain four 32-bit operations for different functional units (integer ALU, FP unit, load/store, branch). Advantages: simpler hardware (no dynamic scheduling), lower power. Disadvantages: heavy compiler burden, binary incompatibility between implementations, NOP padding wastes code space when parallelism is insufficient. Intel Itanium (IA-64/EPIC) was a notable VLIW-like architecture; TI C6000 DSPs are successful VLIW designs.
Q29 What is the difference between in-order and out-of-order execution? ▸
In-order execution processes instructions strictly in program order: if an instruction stalls (e.g., waiting for a cache miss), all subsequent instructions stall too, even if they are independent and could proceed. Out-of-order (OoO) execution allows instructions to execute as soon as their operands are ready, regardless of program order, while maintaining correct program semantics through a reorder buffer (ROB) that commits results in order. OoO requires register renaming, reservation stations, and a ROB, adding significant hardware complexity and power consumption. Simple RISC cores (ARM Cortex-A53) use in-order; high-performance cores (Cortex-A78, Intel Core) use OoO.
Q30 What is Amdahl's Law and how does it apply to CPU design? ▸
Amdahl's Law states that the overall speedup of a system is limited by the fraction of work that cannot be parallelized or improved. Mathematically: Speedup = 1 / ((1 - P) + P/S), where P is the fraction of work that benefits from improvement and S is the speedup of that fraction. In CPU design: if 90% of a program benefits from a 10x speedup, overall speedup is only 1/(0.1 + 0.9/10) = 5.26x, not 10x. This law explains why focusing on common-case performance (RISC philosophy of making common operations fast) is more effective than optimizing rare complex operations. It also limits the returns from increasing core counts in multicore processors.
Q31 How do modern ARM processors compare to x86 in data center workloads? ▸
Modern ARM processors like AWS Graviton3/4, Ampere Altra, and Apple M-series have become competitive with x86 in data centers. Advantages of ARM: (1) Better performance-per-watt due to simpler decode and lower power. (2) Higher core counts (Ampere Altra Max has 128 cores). (3) Custom silicon tailored for specific workloads (Graviton for cloud). (4) Lower licensing costs with RISC-V emerging as open alternative. x86 advantages: (1) Mature software ecosystem and optimization. (2) Superior single-threaded performance in some workloads. (3) AVX-512 for HPC and scientific computing. The trend is toward ARM gaining market share, driven by cloud providers seeking better TCO (total cost of ownership).
Q32 What is the difference between scalar and superscalar processors? ▸
A scalar processor issues and executes one instruction per clock cycle. It has a single pipeline and can achieve at most 1 IPC (instruction per cycle). A superscalar processor can issue and execute multiple instructions per clock cycle by having multiple parallel pipelines and functional units. For example, a 4-wide superscalar processor can fetch, decode, and dispatch up to 4 instructions per cycle. Superscalar execution requires hardware to detect independent instructions (dependency checking), rename registers to eliminate false dependencies, and manage multiple in-flight instructions. Modern high-performance CPUs are typically 4-8 wide superscalar with out-of-order execution.
Q33 What is the role of the Program Counter (PC)? ▸
The Program Counter (PC), also called the Instruction Pointer (IP) in x86, is a special-purpose register that holds the memory address of the next instruction to be fetched and executed. After each instruction fetch, the PC is typically incremented by the instruction size (e.g., +4 bytes for 32-bit RISC instructions). For branch and jump instructions, the PC is loaded with the target address. The PC is fundamental to sequential program execution and is the mechanism by which the processor knows where to find the next instruction. It is saved during interrupts and function calls and restored upon return.
Q34 What is condition code / status register architecture? ▸
A condition code (CC) or status register (also called flags register) architecture uses a special register to record the outcomes of arithmetic/logic operations. Common flags include: Zero (Z) --- result is zero; Negative/Sign (N/S) --- result is negative; Carry (C) --- unsigned overflow; Overflow (V/O) --- signed overflow. Conditional branches test these flags (e.g., BEQ branches if Z=1). x86 uses EFLAGS/RFLAGS; ARM uses CPSR. Pros: compact branch encoding. Cons: creates implicit dependencies between flag-setting and flag-reading instructions, complicating out-of-order execution. MIPS avoided condition codes, using explicit comparison results in registers, simplifying the pipeline.
Q35 What is the difference between EPIC and VLIW? ▸
EPIC (Explicitly Parallel Instruction Computing) is an evolution of VLIW developed by Intel and HP for the Itanium processor. While both rely on the compiler to find parallelism, EPIC adds features to overcome VLIW limitations: (1) Predication --- instructions can be conditionally executed using predicate registers, reducing branches. (2) Speculation support --- hardware for speculative loads and recovery. (3) Instruction groups with explicit stop bits marking dependencies, providing more flexibility than fixed VLIW slots. (4) Register rotation and software pipelining support. VLIW has rigid, fixed-format bundles and requires NOP padding for unused slots. Both approaches struggled to match out-of-order superscalar performance on general-purpose code.
Q36–Q40 Register Files, Microcontrollers & the Fetch Cycle
Q36 What is the register file and how is it organized? ▸
The register file is a small, fast memory array within the CPU that stores the registers accessible by instructions. It is organized as a multi-ported SRAM array where each port allows simultaneous reading or writing. A typical RISC register file with 32 registers needs 2 read ports and 1 write port. In superscalar processors, the register file may have 6-12 read ports and 3-6 write ports. Physical register files in OoO processors are much larger than the architectural register file (e.g., 200+ physical registers for 32 architectural registers) to support register renaming. The register file is the fastest storage in the processor with sub-cycle access time.
Q37 What is the difference between a microprocessor and a microcontroller? ▸
A microprocessor is a CPU on a chip containing only the processing unit (ALU, control unit, registers, cache) and requires external components (memory, I/O controllers). Examples: Intel Core, AMD Ryzen --- used in PCs and servers. A microcontroller integrates the CPU with memory (Flash, SRAM), I/O ports, timers, ADC, and communication interfaces on a single chip. Examples: ATmega328P, STM32, ESP32 --- used in embedded and IoT applications. Microcontrollers optimize for cost, size, and power in real-time control. Microprocessors focus on maximum computational performance.
Q38 What is parity and ECC memory? ▸
Parity adds a single extra bit per byte that records whether the number of 1-bits is even or odd. It can detect single-bit errors but cannot correct them. ECC (Error-Correcting Code) uses multiple check bits (typically SEC-DED: Single Error Correction, Double Error Detection) using Hamming codes to both detect and correct single-bit errors and detect double-bit errors. ECC memory is essential in servers and mission-critical systems. CPUs may use parity in L1 caches for fast error detection and ECC in L2/L3 caches where the latency cost of ECC is proportionally smaller.
Q39 What is the concept of a co-processor? ▸
A co-processor is a supplementary processor designed to handle specific types of operations that the main CPU does not handle efficiently. The CPU offloads these operations to the co-processor, which executes them in parallel. Historical example: the Intel 8087 floating-point co-processor for the 8086 CPU. Modern equivalents include: GPU (graphics and parallel computing co-processor), TPU/NPU (AI/ML inference co-processor), DSP (digital signal processing), and cryptographic accelerators. In ARM, the co-processor interface (CP15 for system control, CP10/CP11 for FP/NEON) provides a standard mechanism for extending processor capabilities. Modern SoCs integrate multiple co-processors for specialized tasks.
Q40 What is the fetch-decode-execute cycle? ▸
The fetch-decode-execute cycle (also called the instruction cycle or machine cycle) is the fundamental operational process of a CPU. It consists of three main phases: (1) Fetch --- the CPU reads the instruction from memory at the address pointed to by the Program Counter (PC), stores it in the Instruction Register (IR), and increments the PC. (2) Decode --- the control unit interprets the instruction, determining the operation and operands, and generates appropriate control signals. (3) Execute --- the ALU or other functional unit performs the specified operation, accessing registers or memory as needed. This cycle repeats continuously, forming the basis of program execution. Pipelining overlaps these phases for different instructions to improve throughput.
Prep Tips for Freshers & Experienced Engineers
For Freshers
- Don't just recite the RISC vs CISC table — be ready to explain *why* each design choice exists (e.g., why RISC uses a load-store architecture to keep pipelines simple).
- Draw the Von Neumann and Harvard diagrams from memory before the interview; being asked to sketch on a whiteboard is common.
- Know at least one real processor example for every concept — ARM/RISC-V for RISC, x86 for CISC, ARM Cortex-M for Harvard architecture.
- Practice explaining endianness with a live example (converting a hex value between big- and little-endian) rather than just the definition.
For Experienced Engineers
- Be ready to connect ISA concepts to your actual project experience — e.g., how instruction encoding choices affected your RTL decoder design or verification plan.
- Interviewers at the senior level often push into micro-architecture vs ISA distinctions and ask you to justify design trade-offs you made, not just describe them.
- Have a point of view on modern trends — why ARM is gaining ground in data centers, or how RISC-V's modularity affects custom accelerator design — since this signals you stay current.
Avoid Common Mistakes
- Confusing ISA with microarchitecture — these are two of the most conflated terms in every interview.
- Giving a one-line RISC vs CISC answer without discussing the underlying design philosophy (compiler complexity vs hardware complexity).
- Forgetting that most modern x86 CPUs internally translate CISC instructions into RISC-like micro-ops — a very common follow-up question.
- Mixing up big-endian and little-endian byte ordering under pressure — always double check with a small worked example.
FAQ Frequently Asked Questions
Is Part 1 enough to clear a fresher-level computer architecture round?
For most campus and entry-level interviews, Part 1 covers the core 40 questions that appear most frequently. Pair it with Part 2 (Pipelining) if the role also touches RTL or verification, since pipelining questions come up almost as often as RISC vs CISC.
Do VLSI and ASIC interviews really ask ISA-level questions, or only RTL questions?
Yes — VLSI and ASIC interviews routinely open with ISA and architecture fundamentals before moving into RTL, pipelining, or verification specifics, because they establish whether you understand what the hardware you're designing or verifying is actually supposed to do.
What's the single most commonly asked question in this set?
RISC vs CISC (Q3–Q5) and the Von Neumann vs Harvard comparison (Q14–Q16) are asked in some form in almost every computer architecture interview, regardless of company or seniority level.
Should I memorize the answers word for word?
No. Interviewers can tell when an answer is memorized. Understand the reasoning behind each answer well enough to explain it in your own words and adapt it if the interviewer changes the question slightly.
How is this different from a generic computer organization course?
This series is written specifically around what gets asked in interviews — phrased as an interviewer would ask, with the depth and examples that separate a pass from a borderline answer.
Wrap-up Conclusion
These 40 questions cover the fundamentals that every computer architecture interview is built on: what an ISA is, how RISC and CISC differ, how Von Neumann and Harvard architectures organize memory, and how registers, endianness, and the fetch-decode-execute cycle fit together. Once these are second nature, you're ready to move into pipelining — where interviews start testing how well you understand performance, not just definitions.
Ready for the next round?
Keep the momentum going — work through all five parts back to back, or jump straight to the topic your next interview is focused on.
Part 2: Continue Learning
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