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Module 6 — Assertions

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VLSI Verification  •  SystemVerilog Series

Module 6 — Assertions



SystemVerilog Assertions (SVA): immediate vs concurrent assertions, properties, sequences, and the implication and repetition operators that let you describe complex temporal protocol behavior declaratively.

🧩 Intermediate → Advanced ⏱ ~22 min read 💻 Code Examples Included

50Immediate Assertions

Immediate assertions are procedural, executed like a statement inside always/initial blocks — they check a boolean expression at the instant they execute, with no notion of time or clocking.

SystemVerilog
always_ff @(posedge clk) begin // basic immediate assertion a_no_x_addr: assert (!$isunknown(addr)) else $error("addr went to X/Z at time %0t", $time); // with explicit pass AND fail actions a_range_check: assert (addr < 16'h1000) $display("addr in range, OK"); // pass action else $fatal(1, "addr out of range: %0h", addr); // fail action end
AspectImmediate AssertionConcurrent Assertion
EvaluationInstant, procedural (like an if-statement)Clock-based, over multiple cycles
Can Describe Sequences?No — single point-in-time checkYes — temporal/multi-cycle behavior
PlacementInside procedural blocks onlyModule-level, procedural blocks, or interfaces
Typical UseSimple sanity/legality checks (no X, in-range)Protocol compliance (req-ack handshakes, pipeline timing)

51Concurrent Assertions

Concurrent assertions describe behavior over time, sampled on a clock edge — they can express "if X happens, then Y must happen within N cycles," making them the tool of choice for protocol checking.

SystemVerilog
// request must be followed by ack within 4 cycles a_req_ack: assert property ( @(posedge clk) disable iff (!rst_n) req |-> ##[1:4] ack ) else $error("ack missing within 4 cycles of req"); // concurrent assertion as a standalone module-level statement // (doesn't need to be inside always/initial) property p_fifo_no_overflow; @(posedge clk) (wr_en && full) |-> 1'b0; endproperty a_no_overflow: assert property (p_fifo_no_overflow); // "cover property" -- NOT a checker, just records whether // the scenario ever occurred (a form of assertion-based coverage) c_back_to_back_wr: cover property ( @(posedge clk) wr_en ##1 wr_en );
💡 disable iff

disable iff (!rst_n) is the standard way to suppress assertion checking during reset — without it, assertions often fire spuriously while the DUT is still in an undefined post-reset state.

52Properties

A property is a named, reusable temporal specification built from boolean expressions, sequences, and implication/logical operators — it's the thing that assert/cover/assume statements check.

SystemVerilog
property p_valid_ready_handshake; @(posedge clk) disable iff (!rst_n) valid && !ready |=> valid; // valid must stay high until ready seen (AXI-style) endproperty property p_one_hot_state; @(posedge clk) $onehot(state_vector); endproperty // properties can take arguments -- reusable across multiple signals property p_max_pulse_width(logic sig, int max_cycles); @(posedge clk) $rose(sig) |-> ##[0:max_cycles] $fell(sig); endproperty // reused for two different signals with different limits assert property (p_max_pulse_width(req, 10)); assert property (p_max_pulse_width(grant, 20));
📘 assert vs assume vs cover

The same property can be used three ways: assert property(p) checks it must hold (bug if violated); assume property(p) tells formal tools/simulators to treat it as a constraint on the environment (used heavily in formal verification); cover property(p) just records whether the scenario ever happened.

53Sequences

A sequence describes an ordered pattern of boolean expressions across clock cycles — the temporal "phrase" building block that properties are constructed from.

SystemVerilog
// basic sequence -- req, then grant exactly 2 cycles later sequence seq_req_grant; req ##2 grant; endsequence // sequence with a variable delay range sequence seq_req_grant_range; req ##[1:5] grant; endsequence // sequences can be combined with 'and' / 'or' / 'intersect' sequence seq_combo; seq_req_grant and (data_valid ##1 data_ready); endsequence // use a sequence inside a property property p_handshake_ok; @(posedge clk) seq_req_grant |-> ##1 ack; endproperty assert property (p_handshake_ok);
💡 Sequences vs Properties

Think of a sequence as a noun phrase ("req followed 2 cycles later by grant") and a property as the full sentence built from one or more sequences plus implication logic ("IF this sequence happens, THEN that must follow"). Sequences alone can't be directly asserted — they need to be wrapped in a property (or used with a bare assert property(seq), which SV allows as shorthand).

54Implication Operators

Implication operators (|-> and |=>) express "if the antecedent (left side) matches, then the consequent (right side) must hold" — the core mechanism for conditional protocol checking.

SystemVerilog
// |-> (overlapped implication) -- consequent checked in the // SAME cycle the antecedent matches property p_overlap; @(posedge clk) req |-> grant; // grant must be high in the SAME cycle as req endproperty // |=> (non-overlapped implication) -- consequent checked // starting the NEXT cycle after the antecedent matches property p_nonoverlap; @(posedge clk) req |=> grant; // grant must be high the cycle AFTER req endproperty // equivalent forms -- |=> is literally shorthand for |-> ##1 property p_equivalent; @(posedge clk) req |-> ##1 grant; // same as "req |=> grant" endproperty // chained implications for multi-step protocols property p_full_txn; @(posedge clk) req |=> grant ##1 (valid throughout (data_beat[0:3])); endproperty
OperatorNameConsequent Checked
|->Overlapped implicationSame clock cycle as the antecedent match
|=>Non-overlapped implicationStarting one cycle after the antecedent match
🚫 Interview Favorite

"Explain the difference between |-> and |=>" is one of the single most common SVA interview questions. Remember: |=> is exactly equivalent to |-> ##1 — non-overlapped just adds one implicit cycle of delay before checking the consequent.

55Repetition Operators

Repetition operators let a sequence match a signal holding a value (or matching a sub-sequence) a specific or variable number of times — essential for expressing burst/back-pressure protocol behavior concisely.

SystemVerilog
// [*n] -- consecutive repetition, exactly n times sequence seq_busy_4cyc; busy[*4]; // busy must be high for exactly 4 CONSECUTIVE cycles endsequence // [*n:m] -- consecutive repetition, between n and m times sequence seq_busy_range; busy[*2:6]; // busy high for 2 to 6 consecutive cycles endsequence // [->n] -- goto repetition: matches on the nth time the // expression becomes true, WITHOUT requiring consecutive cycles sequence seq_3rd_ack; ack[->3]; // waits until ack has pulsed high a 3rd time (non-consecutive OK) endsequence // [=n] -- non-consecutive repetition (like goto but doesn't // anchor the sequence end to the matching cycle) sequence seq_err_seen_twice; err[=2] ##1 recovery_done; // err must occur (non-consecutively) exactly // twice at SOME point before recovery_done endsequence // combined with implication for a full burst-check property property p_burst_of_8; @(posedge clk) start_burst |=> valid[*8] ##1 !valid; endproperty
OperatorNameMeaning
[*n]Consecutive repetitionExpression true for exactly n consecutive cycles
[*n:m]Consecutive range repetitionTrue for between n and m consecutive cycles
[->n]Goto repetitionMatches at the nth occurrence, non-consecutive allowed
[=n]Non-consecutive repetitionExpression true exactly n times, non-consecutively, without anchoring sequence end there
💡 Interview Tip

"Difference between [->n] and [=n]?" — Both allow non-consecutive matches, but [->n] anchors the sequence's completion to the exact cycle of the nth match (so anything chained after it with ## counts from there), while [=n] just requires n occurrences somewhere within the overall sequence window, without anchoring.

🎯 Module 6 Recap

  • Immediate assertions check a condition instantly and procedurally; concurrent assertions check temporal behavior over clock cycles.
  • property is the full checkable specification; sequence is a reusable temporal building block used inside properties.
  • |-> checks the consequent in the same cycle; |=> checks it starting the next cycle (equivalent to |-> ##1).
  • Repetition operators ([*n], [*n:m], [->n], [=n]) compactly express consecutive vs non-consecutive repeated matches.
  • The same property can be used with assert (must hold), assume (treat as environment constraint, esp. in formal), or cover (just record occurrence).

📚 Next up — Module 7: Interfaces (interface, modports, clocking blocks, virtual interface)

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