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OpenAI's Custom AI ASIC: Why the Industry Is Moving Beyond GPUs
Inference is no longer a research cost — it is a utility bill. That single economic fact is pushing every frontier AI company from general-purpose GPUs toward purpose-built silicon. Here is the engineering behind the shift.
For a decade, "AI compute" and "GPU" were treated as synonyms. That equivalence was never a law of physics — it was an accident of history. The GPU won because it was already there: a massively parallel, high-bandwidth, floating-point machine with a mature software stack, sitting on a shelf at exactly the moment deep learning needed one.
But a chip that is excellent at everything parallel is, by construction, not optimal at one specific thing. And in 2026, the industry has converged on one specific thing that dominates the electricity bill: autoregressive transformer inference at hyperscale.
On 24 June 2026, OpenAI and Broadcom unveiled Jalapeño — OpenAI's first custom accelerator, an ASIC designed from a blank sheet purely for LLM inference. It is not a repurposed training part and not a general-purpose AI processor. It went from initial design to tape-out in roughly nine months, which the two companies describe as the fastest ASIC development cycle ever achieved in high-performance advanced semiconductors, with OpenAI's own models assisting parts of the design and optimization flow.
This article is not a press release summary. It is a design-engineer's walkthrough of why the GPU is a poor fit for decode-phase inference, what an inference ASIC actually changes at the microarchitecture level, and what that means if you build chips for a living.
What's Inside
- The inference economy: why silicon strategy changed
- Prefill vs decode — two workloads wearing one costume
- The memory wall, with real numbers
- Why a GPU leaves performance on the table
- Jalapeño: what OpenAI and Broadcom actually built
- Anatomy of an LLM inference ASIC
- Numerics: FP8, MXFP4 and precision as microarchitecture
- The interconnect is half the chip
- The competitive landscape: TPU, Trainium, Maia, MTIA
- What breaks: the honest risks of custom silicon
- What this means for VLSI engineers
- Recap
1. The Inference Economy: Why Silicon Strategy Changed
Training a frontier model is a large, lumpy capital expense. You do it once, you amortize it, you move on. Inference is different in kind: it is a marginal cost that scales linearly with product success. Every additional user, every additional token, every additional reasoning step in an agentic loop draws current from a rack somewhere.
Three things happened at once to make this the dominant design constraint:
- Reasoning models changed the token profile. Chain-of-thought and agentic workflows generate enormous quantities of intermediate tokens the user never sees. Output-token volume per user request grew by an order of magnitude while pricing pressure went the other way.
- Inference overtook training as the majority of AI compute. Industry analyses through 2026 put inference at roughly two-thirds of total AI compute demand — the workload mix inverted.
- Hardware gross margin became a strategic liability. When a single supplier holds most of the accelerator market, its margin is a permanent tax on your unit economics. Hyperscalers building in-house silicon regularly cite 40–65% total-cost-of-ownership advantages on the workloads they control end to end.
Frontier AI infrastructure is no longer optimized for peak FLOPS. The operative figures are cost per million output tokens and tokens per second per watt at a fixed latency target. Both are dominated by data movement, not arithmetic. Hold that thought — it explains nearly every architectural decision below.
2. Prefill vs Decode — Two Workloads Wearing One Costume
The single most important thing to understand about LLM serving is that "inference" is really two different computations with opposite hardware appetites.
Prefill (prompt processing)
The entire input sequence is available at once. You compute Q, K, V for all S tokens in parallel. Every weight matrix you fetch from HBM gets reused across S tokens. This is a GEMM-shaped, compute-bound workload — exactly what tensor cores and systolic arrays were built for. Utilization can be high.
Decode (token generation)
Now you generate one token at a time. Each step, the model must read every weight in the model plus the entire KV cache from memory — and then perform arithmetic on a batch of size B with sequence length 1. The GEMM has collapsed into a GEMV (matrix–vector product). Weight reuse is limited to the batch dimension alone.
That result is brutal in its simplicity: during decode, arithmetic intensity is proportional to batch size and nothing else. At B = 32 with FP8 weights, you are operating at roughly 64 FLOPs per byte. A modern GPU needs intensity in the several-hundreds to saturate its FLOPs. You are memory-bound by a wide margin, and the expensive floating-point silicon you paid for sits idle waiting on HBM.
The obvious fix — batch harder — collides with two walls. First, latency: interactive and agentic products have strict time-to-first-token and inter-token-latency budgets, and large batches inflate queueing delay. Second, KV cache capacity: cache size grows linearly with batch × context length, and long-context reasoning workloads consume HBM that you wanted for weights. Batching is a knob with a short travel range.
3. The Memory Wall, With Real Numbers
Let's make this concrete. Take a hypothetical dense 70B-parameter model served in FP8, with 80 layers, 64 query heads, 8 KV heads (grouped-query attention), and head dimension 128.
Weight traffic per decode step
KV cache traffic per decode step
= 2 × 80 × 8 × 128 × 8192 × 32 × 1 B ≈ 34.4 GB
So a single token of output — for a batch of 32 at 8K context — requires roughly 104 GB of memory traffic. On an accelerator delivering 8 TB/s of usable HBM bandwidth, that is about 13 ms per token, i.e. ~77 tokens/s aggregate across the batch, or ~2.4 tokens/s per user. Meanwhile the arithmetic performed is about 4.5 TFLOP — which a 2 PFLOP-class part would finish in ~2.2 ms.
In this scenario the compute pipeline is idle roughly 83% of the time. You are not buying FLOPS. You are buying bandwidth, and paying for FLOPS you cannot use. Every serious inference-ASIC decision — HBM stack count, on-die SRAM capacity, dataflow, quantization format, attention kernel structure — is a direct attack on this ratio.
Here is the same reasoning as a reusable roofline sanity-check you can run against any candidate architecture:
# Quick TCO-relevant roofline for autoregressive decode.
def decode_step(params_B, bytes_w, layers, kv_heads, head_dim,
seq_len, batch, bw_TBs, flops_PF):
w_bytes = params_B * 1e9 * bytes_w
kv_bytes = 2 * layers * kv_heads * head_dim * seq_len * batch * bytes_w
total_B = w_bytes + kv_bytes
flops = 2 * batch * params_B * 1e9 # GEMV dominates
intensity= flops / total_B # FLOPs per byte
t_mem = total_B / (bw_TBs * 1e12)
t_cmp = flops / (flops_PF * 1e15)
return {
"traffic_GB" : total_B / 1e9,
"intensity" : intensity,
"bound" : "MEMORY" if t_mem > t_cmp else "COMPUTE",
"ms_token" : 1e3 * max(t_mem, t_cmp),
"util_pct" : 100 * t_cmp / max(t_mem, t_cmp),
}
print(decode_step(70, 1, 80, 8, 128, 8192, 32, 8.0, 2.0))
# -> traffic ~104 GB, intensity ~43 FLOP/B, bound MEMORY, ~17% compute util
4. Why a GPU Leaves Performance on the Table
None of this means GPUs are badly designed. It means they are designed for a superset of the problem, and generality has a silicon cost. Concretely:
- Dark silicon for unused functions. Raster pipelines, texture units, broad FP64 capability, graphics fixed-function blocks, and a fully general warp scheduler all consume area and leakage that an inference-only part simply does not instantiate.
- SIMT overhead. Fetch, decode, scoreboard, register-file bank arbitration and dynamic scheduling are re-executed for every warp, every cycle. A systolic or dataflow engine amortizes control across a whole tile — the operands march through the array and the control cost per MAC approaches zero.
- Register-file energy. In a GPU, tensor-core operands are staged through a large multi-ported register file. In a weight-stationary systolic array, a weight is loaded once and reused across the entire streaming dimension. Moving a byte across the die costs orders of magnitude more energy than the multiply itself — so where operands live is the power decision.
- Memory hierarchy tuned for the wrong reuse pattern. Cache hierarchies optimized for irregular, latency-sensitive access are the wrong shape for a workload whose access pattern is perfectly known at compile time. A software-managed scratchpad with a compiler-generated schedule beats a hardware cache when the schedule is static.
- Fixed compute:bandwidth ratio. A GPU vendor must pick one ratio for training and inference, big models and small, prefill and decode. An ASIC designer who serves exactly one model family can pick the ratio that maximizes throughput per watt for that family — and rebalance it next generation.
A GPU spends transistors on flexibility you might need. An inference ASIC spends the same transistors on bandwidth, on-die memory, and MACs you definitely need. When the workload is stable and enormous, the second trade wins on every axis that appears in a datacenter P&L.
5. Jalapeño: What OpenAI and Broadcom Actually Built
Public technical detail is still thin — OpenAI has said a fuller technical report will follow — but the disclosed architecture-level choices are unusually informative because each one maps cleanly onto the bottlenecks above.
| Disclosed characteristic | Engineering interpretation |
|---|---|
| Purpose-built inference ASIC — explicitly not a repurposed training accelerator or general-purpose AI processor | The compute:bandwidth ratio, numeric formats and dataflow can be tuned for decode-dominant serving rather than hedged across training. No gradient path, no optimizer state, no training-scale collectives. |
| Large reticle-scale compute chiplet paired with HBM, rather than cheaper DRAM used by some inference parts | A deliberate refusal to trade bandwidth for cost. If decode is bandwidth-bound, cheaper DRAM caps your tokens/s per accelerator no matter how many MACs you build. HBM is the enabling technology for low-latency reasoning workloads. |
| Architected around costly data movement and compute/memory balance | Confirms the roofline framing: the design target is energy per byte moved and effective utilization, not headline peak FLOPS. |
| Both high throughput and low latency, aimed at reasoning and agentic workloads | Agentic loops are latency-serial: step N+1 cannot start until step N returns. Batching alone cannot rescue these, so per-token latency is a first-class design constraint. |
| Effective utilization near theoretical maximum, per OpenAI/Broadcom claims | The most telling claim of the set. Utilization — not peak — is the entire game in decode. It implies deep co-design between the kernel/compiler stack and the memory scheduler. |
| Broadcom supplies silicon implementation, networking and connectivity; TSMC manufactures; Celestica handles board, rack and system integration | Classic modern ASIC division of labour: the model owner defines microarchitecture and numerics; the ASIC partner owns physical implementation, SerDes/IP and scale-up fabric; the ODM owns thermal and rack integration. |
| ~9 months concept to tape-out, with OpenAI models assisting design and optimization | Extraordinary for a reticle-class part. It implies aggressive hardened-IP reuse, a highly constrained feature set, ML-assisted PPA optimization in place-and-route, and an emulation-first verification strategy. |
| Engineering samples already running production-target workloads in lab; performance/watt reported substantially ahead of current state of the art | First-silicon bring-up running real models is a strong signal for the verification methodology. Treat the perf/W figure as vendor-reported until independent benchmarks land. |
Deployment is planned to begin by the end of 2026 as the first step in a multi-generation platform, and the partnership is framed around gigawatt-scale datacenter buildout. Notably, OpenAI is not abandoning GPUs — the public strategy runs custom silicon, commercial accelerators and GPUs in parallel.
Custom silicon here is not principally about beating a GPU on a benchmark. It is about vertical integration: owning the stack from product to model to kernel to RTL, so that model architecture and hardware architecture can be co-designed on the same roadmap. When you control both sides, you can make choices — a numeric format, an attention layout, a sparsity pattern — that neither side could adopt alone.
6. Anatomy of an LLM Inference ASIC
Strip away branding and virtually all modern inference accelerators share the same five-block skeleton. Understanding it lets you read any of these announcements critically.
6.1 The matrix engine
A dense array of multiply-accumulate cells, typically arranged as a weight-stationary systolic array or a tiled dataflow engine. Weights are loaded into the cells; activations stream through; partial sums propagate. The control cost per MAC is amortized across the whole array — this is the primary energy advantage over SIMT.
// One processing element of an output-stationary-accumulate,
// weight-stationary systolic array. Activations flow east,
// partial sums flow south. Registered on all edges for timing.
module pe_mac #(
parameter int AW = 8, // activation width (FP8/INT8)
parameter int WW = 8, // weight width
parameter int ACCW = 32 // accumulator width
)(
input logic clk, rst_n,
input logic w_load, // latch new weight tile
input logic en, // clock-gate enable
input logic [WW-1:0] w_in,
input logic [AW-1:0] a_in, // from west
input logic [ACCW-1:0] psum_in, // from north
output logic [AW-1:0] a_out, // to east
output logic [ACCW-1:0] psum_out // to south
);
logic [WW-1:0] w_reg;
// Weight stays resident across the whole streaming dimension —
// this is where the energy saving over a register-file machine lives.
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) w_reg <= '0;
else if (w_load) w_reg <= w_in;
end
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
a_out <= '0;
psum_out <= '0;
end else if (en) begin
a_out <= a_in; // systolic hop
psum_out <= psum_in + ($signed(a_in) * $signed(w_reg));
end
end
endmodule
The verification of such an array is dominated not by the PE — which is trivial — but by the skew discipline: activations and partial sums must arrive at each cell with exactly the right relative delay. A single misaligned pipeline stage silently corrupts every result. Assertions are the cheapest place to catch it:
// 1. A weight load must never coincide with an active MAC pass,
// or the array mixes two weight tiles in one result.
property p_no_load_during_stream;
@(posedge clk) disable iff (!rst_n)
w_load |-> !stream_active;
endproperty
a_no_load_during_stream : assert property (p_no_load_during_stream)
else $error("Weight tile reloaded mid-stream: results corrupted");
// 2. Activation entering column 0 must appear at column N-1
// after exactly N-1 cycles — proves the systolic skew is intact.
property p_skew_latency;
@(posedge clk) disable iff (!rst_n)
(en && a_valid_in) |-> ##(N-1) a_valid_out;
endproperty
a_skew_latency : assert property (p_skew_latency);
// 3. Accumulator must not silently wrap. In low-precision inference
// this is a real hazard, not a theoretical one.
property p_no_acc_overflow;
@(posedge clk) disable iff (!rst_n)
en |-> !acc_overflow;
endproperty
a_no_acc_overflow : assert property (p_no_acc_overflow)
else $error("Accumulator overflow — widen ACCW or rescale");
6.2 The memory subsystem
Two tiers, and the split between them is the highest-leverage decision on the chip:
- HBM — holds weights and the KV cache. Stack count and generation set your decode ceiling. This is why choosing HBM over commodity DRAM, as Jalapeño reportedly does, is an architecture statement rather than a bill-of-materials detail.
- On-die SRAM / scratchpad — tens to hundreds of megabytes, software-managed. Bigger SRAM means more of a layer's working set stays on die, which cuts HBM traffic and therefore energy. But SRAM area does not scale well at advanced nodes, and it competes directly with MAC area for reticle budget.
6.3 The attention and vector units
Softmax, RoPE, RMSNorm, GELU/SwiGLU, top-k sampling and KV-cache gather are not GEMMs. Attention in particular has an awkward access pattern that punishes naive designs. Modern inference ASICs harden fused, online-softmax attention (FlashAttention-style tiling) so that the entire attention block executes without round-tripping intermediates to HBM.
6.4 Sequencing and control
Usually a small cluster of general-purpose cores (frequently RISC-V) that runs the schedule, manages descriptors, drives DMA and handles the sampling loop. Modest silicon; disproportionate influence on achieved utilization.
6.5 The network interface
SerDes, scale-up fabric and collective-operation engines. Because frontier models exceed a single package, some fraction of every token's latency is spent on the wire. See §8.
7. Numerics: FP8, MXFP4 and Precision as Microarchitecture
Quantization is the most direct lever on the memory wall, because bytes per parameter appears in the denominator of arithmetic intensity. Halving weight precision roughly halves decode-step traffic — a near-linear throughput win on a bandwidth-bound workload.
| Format | Bits | Structure | Where it fits | Hardware implication |
|---|---|---|---|---|
| BF16 | 16 | 1 / 8 / 7 | Training, accumulation, sensitive layers | Wide multipliers; baseline reference |
| FP8 (E4M3) | 8 | 1 / 4 / 3 | Weights and activations in serving | Per-tensor or per-channel scaling; needs scale broadcast paths |
| FP8 (E5M2) | 8 | 1 / 5 / 2 | Wider-dynamic-range tensors | Dual-format MAC support adds mux cost |
| INT8 | 8 | Integer | Well-calibrated weights | Cheapest MAC; requires robust calibration flow |
| MXFP4 / block FP4 | 4 (+shared exp) | Micro-block scaling | Aggressive weight-only compression | Block-scale decode logic in the datapath; 2× traffic reduction vs FP8 |
| KV cache INT8/FP8 | 8 | Per-token or per-head scale | Long-context serving | Attention unit must dequantize inline at full rate |
Low precision is a genuine win right up to the point where it isn't. Accumulation almost always stays at FP32 or wide fixed-point. Outlier channels in activations resist naive per-tensor scaling. And the moment your ASIC hardens a specific block-scaling format, you have made a bet that the next model generation still trains well in it. That bet is the central risk of the whole approach — see §10.
The design-time consequence: a custom inference part usually supports a narrow set of formats extremely efficiently, rather than a wide set adequately. Every format you drop is area and leakage you convert into MACs or SRAM.
8. The Interconnect Is Half the Chip
A frontier model does not fit in one package. Tensor parallelism splits individual matrix multiplies across accelerators, which means an all-reduce sits inside the critical path of every single layer. At 80 layers and one token at a time, collective latency is multiplied 80× per token. This is why OpenAI's announcement puts networking efficiency alongside data movement as a first-order design target, and why Broadcom — a networking company as much as an ASIC house — is the partner.
- Scale-up domain: a tightly coupled group of accelerators with high-bandwidth, low-latency, often load/store-coherent links. Tensor parallelism lives here. The size of this domain is arguably the most important system-level number in an inference platform.
- Scale-out domain: Ethernet-class fabric across racks. Pipeline parallelism, expert parallelism for MoE, and request routing live here. Latency tolerance is higher.
- On-package: chiplet-to-chiplet links (UCIe-class) and 2.5D/3D advanced packaging. Note that advanced packaging capacity — not wafer starts — is frequently the binding constraint on how many of these parts anyone can actually ship.
When you read any inference accelerator spec, look past peak FLOPS to three numbers: HBM bandwidth per accelerator, scale-up bandwidth per accelerator, and the size of the coherent scale-up domain. Those three, plus supported numeric formats, predict decode throughput far better than the headline compute figure.
9. The Competitive Landscape
OpenAI is a late entrant to a movement that has been building for a decade. The 2026 picture:
| Program | Owner | Focus | Status & notes |
|---|---|---|---|
| TPU (v7 Ironwood and successors) | Training + inference | The oldest program — roughly a decade of compounding investment; deployed at the largest custom-silicon volume of any hyperscaler | |
| Trainium 3 | Amazon / Annapurna | Training + inference | 3nm generation ramping through 2026; Trainium 4 announced; accessed through AWS instances only |
| Maia 200 | Microsoft | Inference | Deployed in Azure to serve first-party and API traffic; not externally rentable as raw hardware |
| MTIA family | Meta | Inference (ranking + GenAI) | Multiple new parts revealed in 2026; later generations add substantially more HBM for generative workloads |
| Jalapeño | OpenAI + Broadcom | LLM inference only | Unveiled June 2026; deployment targeted from end of 2026; first of a multi-generation platform |
| Vera Rubin | NVIDIA | General-purpose response | The incumbent's counter: FP4-class throughput with HBM4 and a mature software ecosystem |
| Groq, Cerebras, Etched, others | Merchant | Niche inference | Around 1% combined share, but real wins in latency-extreme or transformer-specific niches |
Two structural observations are worth more than the table itself.
First: one design house sits under almost all of it. Broadcom is the ASIC design partner across a striking share of these programs, with estimates putting it near 60% of AI-server compute-ASIC design partnerships. The company that captures durable margin from custom silicon is frequently not the company whose name is on the chip.
Second: NVIDIA's share is falling while its revenue sets records. Both are true simultaneously because the market roughly doubled underneath it. 2026 revenue-share estimates cluster around 73–85% for NVIDIA, down from over 90% a few years earlier, with custom silicon growing far faster than the market. For anyone who is not a hyperscaler, the practical choice remains NVIDIA or AMD — TPUs, Trainium, Maia, MTIA and Jalapeño are captive parts, not merchant products.
10. What Breaks: The Honest Risks of Custom Silicon
Silicon takes years to design and years to depreciate. Model architectures move in months. Harden the wrong assumption — a specific attention pattern, an MoE routing scheme, a numeric format, a maximum context length — and your fleet becomes an expensive, efficient machine for running a model nobody serves anymore. This is why sensible inference ASICs harden the stable primitives (GEMM, softmax, normalization, elementwise) and keep the composition programmable.
Two decades of CUDA, cuDNN, NCCL, TensorRT-LLM, vLLM, SGLang and FlashAttention kernels do not port for free. Every custom accelerator needs its own compiler, kernel library, collective library, profiler and debugger — and needs them to keep pace with a research community that ships new kernels weekly. Silicon is arguably the easier half of the project.
Essentially every advanced AI accelerator is fabricated at TSMC, which produces around 92% of AI silicon at 7nm and below. Leading-edge nodes and advanced packaging run at full utilization with demand well above supply. A brilliant design that cannot secure CoWoS-class packaging slots ships nothing.
A reticle-class ASIC at a leading node carries mask, IP, EDA, engineering and bring-up costs in the hundreds of millions before the first good die. That amortizes beautifully across a million units and catastrophically across ten thousand. Custom silicon is a strategy available only to organizations whose own workload is large enough to fill the fab slot.
This is precisely why the credible players run dual-track strategies: custom silicon for the predictable, high-volume, well-characterized inference workload; merchant GPUs for training, experimentation, burst capacity and anything whose shape is still changing.
11. What This Means for VLSI Engineers
The strategic story is interesting. The career story is more actionable. A structural shift toward custom AI silicon changes what skills are scarce.
Architecture and microarchitecture
- Roofline and analytical performance modelling — being able to argue from arithmetic intensity, bandwidth and utilization rather than from peak numbers.
- Dataflow taxonomy: weight-stationary, output-stationary, row-stationary, and the energy consequences of each.
- Memory-hierarchy design under a fixed reticle budget: the SRAM-versus-MAC area trade is the recurring argument in every one of these projects.
RTL and physical design
- Large, highly regular arrays with tight timing closure and severe local power density — systolic arrays are a floorplanning and IR-drop problem as much as a logic problem.
- Fine-grained clock gating and power gating; multi-VT and multi-corner signoff where leakage is a first-order cost.
- Chiplet partitioning, die-to-die IP, and 2.5D/3D packaging-aware physical design.
- HBM PHY integration, controller scheduling, refresh management and thermal interaction with the compute die.
Verification
- Numerical equivalence checking against a golden model — bit-accurate reference models for FP8/MXFP4 datapaths, and the tolerance policy for what "matching" means.
- Emulation and prototyping at a scale where you run real model layers, not directed tests. A nine-month tape-out cycle is only achievable with an emulation-first methodology.
- Performance verification as a discipline in its own right: proving achieved utilization, not just functional correctness.
- Assertion-heavy design for dataflow correctness, as illustrated in §6.1.
The hybrid skill that is genuinely scarce
The scarcest engineer in this market is the one who can read a transformer implementation and a timing report in the same afternoon — who understands why grouped-query attention changes the KV-cache bandwidth equation and what that implies for HBM channel count. Hardware/software co-design is not a buzzword here; it is the entire competitive advantage of the approach.
Take a model you know, compute its decode-phase arithmetic intensity by hand for two or three batch sizes and context lengths, and identify the exact point where it crosses from memory-bound to compute-bound. That one exercise teaches more about AI accelerator design than any number of architecture diagrams — and it is a question that comes up in interviews for these teams.
📌 Recap
- Inference, not training, is now the dominant cost — roughly two-thirds of AI compute — which makes cost per token the metric that drives silicon strategy.
- Decode is memory-bound. Arithmetic intensity scales only with batch size, so expensive FLOPS sit idle waiting on HBM. Every ASIC decision attacks that ratio.
- GPUs pay a generality tax: unused fixed-function blocks, SIMT control overhead, register-file energy, and a compute:bandwidth ratio hedged across many workloads.
- Jalapeño — OpenAI's first custom accelerator, built with Broadcom, fabricated by TSMC — is explicitly inference-only, uses a large compute chiplet with HBM rather than cheaper DRAM, and targets high effective utilization at low latency. Tape-out in about nine months; deployment from end of 2026.
- The skeleton is consistent across TPU, Trainium, Maia, MTIA and Jalapeño: matrix engine, two-tier memory, hardened attention/vector units, a control cluster, and a serious scale-up fabric.
- Numerics are microarchitecture. FP8 and block-FP4 cut decode traffic almost linearly — but hardening a format is a bet on future model training recipes.
- The real risks are software, model churn, packaging capacity and volume economics — which is why everyone runs custom silicon and GPUs in parallel rather than switching outright.
- For engineers: roofline reasoning, dataflow design, HBM/chiplet integration, low-precision datapath verification and hardware-software co-design are the scarce skills of the next cycle.
⚡ Next Up
Inside the Systolic Array: Designing a Matrix Engine in SystemVerilog. We build a parameterized weight-stationary array from PE to tile controller — dataflow scheduling, skew discipline, accumulator sizing for FP8, clock-gating strategy, and the SVA suite that catches the failures simulation waveforms will not show you.
Note: performance figures attributed to vendors are as reported at announcement and await independent benchmarking. Worked numerical examples use a hypothetical model configuration for illustration.
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