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Fusion Compiler Overview

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Fusion Compiler Overview | The Silicon Stack
EDA Tools & Industry Guidance · Part 8

Fusion Compiler: Unifying Synthesis and Place-and-Route

Why Synopsys merged Design Compiler and ICC2 into one data model, and a real fc_shell RTL-to-GDSII run.

In this post

  1. 1. Overview
  2. 2. Use Case & Who It's For
  3. 3. Where It Sits in the Design Flow
  4. 4. Installation & Licensing
  5. 5. Hands-On Example: A Unified RTL-to-GDSII Run
  6. 6. Key Takeaways

1.Overview

Fusion Compiler is Synopsys's unified RTL-to-GDSII implementation tool. Instead of running Design Compiler and IC Compiler II as two separate tools that hand off a netlist file, Fusion Compiler combines synthesis and place-and-route into one product on a single, shared data model — in practice, Fusion Compiler = Design Compiler's synthesis engines + IC Compiler II's physical engines, sharing one in-memory design representation instead of two.

Note Fusion Compiler doesn't replace Design Compiler or ICC2 as separate products — some teams still run them as discrete synthesis and place-and-route stages, particularly for very large hierarchical flows with established sign-off methodologies. Fusion Compiler is Synopsys's fastest path when a team can adopt the unified flow end to end.

2.Use Case & Who It's For

Fusion Compiler targets teams who want to minimize iteration between synthesis and physical implementation:

  • Advanced-node SoC teams where synthesis-to-layout correlation gaps cost real schedule time across multiple iterations
  • Design teams adopting AI-driven optimization (Synopsys DSO.ai) that benefits from a single, consistent data model across the full RTL-to-GDSII flow
  • Projects prioritizing fastest time-to-results over the more modular, stage-by-stage control that separate Design Compiler / ICC2 runs offer

3.Where It Sits in the Design Flow

Fusion Compiler collapses what would otherwise be two flow stages into one:

  1. Verified RTL and SDC constraints are read directly into Fusion Compiler — no separate netlist hand-off step
  2. Synthesis and physical implementation run within the same tool instance, sharing floorplan and timing data live instead of re-deriving it after each hand-off
  3. Physical synthesis optimization blurs the line between "logic synthesis" and "placement-aware optimization," since both operate on the same data model simultaneously
  4. The resulting routed design is extracted (StarRC) and handed to PrimeTime for the same golden signoff step used in a Design Compiler + ICC2 flow
  5. ECOs and incremental changes can be applied without re-running two separate tools in sequence
Industry Insight The core motivation behind Fusion Compiler isn't a new algorithm so much as removing a data hand-off: every time synthesis and place-and-route are separate tools, timing estimates made during synthesis can drift from what placement and routing actually achieve, forcing extra iterations to converge. Sharing one data model directly targets that drift.

4.Installation & Licensing

  1. Download the Fusion Compiler installer from Synopsys SolvNetPlus, under the Galaxy Design Platform agreement (Fusion Compiler is typically licensed as its own product, distinct from standalone Design Compiler and ICC2 licenses)
  2. Install on supported 64-bit Linux, sharing the common Synopsys installation tree used by PrimeTime, Design Compiler, and ICC2
  3. Configure the Synopsys FlexLM license server and SNPSLMD_LICENSE_FILE
  4. Source the environment setup so fc_shell resolves on PATH
  5. As with ICC2, foundry-supplied technology files (LEF, library views, DRC/LVS decks) are required and are distributed separately under your foundry NDA

5.Hands-On Example: A Unified RTL-to-GDSII Run

A minimal Fusion Compiler session going from RTL straight through to a routed design, without a separate synthesis-to-place-and-route file hand-off:

# fc_flow.tcl - unified RTL-to-GDSII flow
create_lib top_lib -tech tech.tf -ref_libs {ref_libs.list}
read_verilog -sv {counter.sv top.sv}
current_design top
read_sdc constraints.sdc

# Synthesis and floorplanning share the same data model here
initialize_floorplan -core_utilization 0.70
compile_fusion -to_placement

clock_opt -to final
route_auto

extract_rc
report_timing -delay_type max -nworst 3

write_verilog top_routed.v
write_parasitics -output top_routed.spef

Notice there's no explicit "write netlist, then read it back into a different tool" step between synthesis and placement — compile_fusion -to_placement carries the design straight from RTL through synthesis into a placed state within the same session, which is exactly the hand-off Fusion Compiler is built to remove.

Tip If you're coming from a separate Design Compiler + ICC2 background, resist the urge to mentally split a Fusion Compiler run into "the DC part" and "the ICC2 part." Constraints and floorplan decisions you'd normally set only once, at hand-off, now influence synthesis directly — get your floorplan reasonably right before the first full run.

Recap

  • Fusion Compiler = Design Compiler's synthesis engines + ICC2's physical engines, one shared data model.
  • It removes the netlist hand-off between synthesis and place-and-route, reducing timing-correlation drift.
  • It's licensed and run as its own product, distinct from standalone Design Compiler / ICC2 flows.
  • Core flow: read RTL/SDC → floorplan → compile_fusion -to_placement → clock_opt → route_auto.
Coming Up in the Series

Company-level overviews of Cadence, Synopsys, and Siemens EDA, plus dedicated posts on tool installation guides and learning roadmaps across the EDA stack.

EDA Tools & Industry Guidance · Series
← ICC2
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