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Xcelium Simulator Overview

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Xcelium Simulator Overview | The Silicon Stack
EDA Tools & Industry Guidance · Part 3 of 4

Xcelium: Cadence's Parallel Logic Simulator

How Xcelium's Apps model and xrun workflow differ from Questa, and why parallel build matters for large regressions.

In this post

  1. 1. Overview
  2. 2. Use Case & Who It's For
  3. 3. Where It Sits in the Verification Flow
  4. 4. Installation & Licensing
  5. 5. Hands-On Example: An xrun Regression
  6. 6. Key Takeaways

1.Overview

Xcelium is Cadence's parallel logic simulator, positioned as the industry's first production-proven parallel-computing simulator when it launched, built around multi-core parallel build and execution rather than a single-threaded kernel. It supports SystemVerilog, VHDL, SystemC, the e language, UVM, mixed-signal, low-power, and X-propagation verification.

Cadence extends Xcelium through a set of domain-specific Xcelium Apps — mixed-signal, multi-core, machine-learning-driven regression (SimAI), and functional safety — rather than bundling every capability into one monolithic license.

Note A newer Xcelium Distributed Simulation App accelerates multi-die/chiplet-level simulation by distributing the workload, reportedly up to 3x faster on multi-die systems — directly aimed at the chiplet and 3DIC verification problem rather than classic single-die SoC work.

2.Use Case & Who It's For

Xcelium shows up wherever Cadence's broader verification ecosystem (Palladium emulation, Jasper formal, Verisium debug) is already in use, and specifically for:

  • Large SoC and IP-level UVM simulation where multi-core parallel build/run reduces wall-clock time
  • Mixed-signal verification, co-simulating digital SystemVerilog with analog Spectre SPICE blocks
  • Machine-learning-assisted regression via the SimAI App, which builds models from past regressions to target new tests and hunt "cousin bugs" related to known failures
  • Functional safety verification flows requiring fault injection and safety mechanism checks

3.Where It Sits in the Verification Flow

Xcelium occupies the same conceptual slot as Questa in a UVM flow — it's the simulation kernel executing your testbench — but with a workflow built around a single driver command:

  1. RTL and UVM testbench sources are organized into a filelist
  2. xrun handles compile, elaborate, and simulate as one invocation (or as separate staged steps for large regressions)
  3. Xcelium's incremental and parallel build features avoid recompiling unchanged sources across regression runs
  4. Failures are debugged in the Cadence Verisium (formerly SimVision) waveform and debug environment
  5. The SimAI App can be layered on top of an existing regression database to synthesize new targeted tests without hand-writing them
Industry Insight "Cousin bug hunting" in SimAI is a good example of where verification is heading: instead of only reproducing a known failure, the tool uses information from that failure to guess at structurally similar tests likely to expose related, undiscovered bugs.

4.Installation & Licensing

  1. Download the Xcelium installer from Cadence's support portal (requires a Cadence account tied to your organization's license agreement — there is no free general-use edition)
  2. Install on a supported 64-bit Linux distribution; Cadence tools are commonly deployed via a shared network install referenced by multiple engineers rather than per-machine installs
  3. Configure the Cadence License Manager (based on FlexLM) to point at your organization's license server
  4. Source Cadence's environment setup script (commonly wrapped in a company-standard module load or shell alias) so xrun resolves on your PATH
  5. For learning without an install, Cadence and third parties occasionally provide trial access or browser-based practice environments (e.g., EDA Playground) using Xcelium under the hood
Watch Out For There is no fully free, full-featured Xcelium edition for general use — unlike Vivado's BASIC tier. Budget for licensing or lean on university/EDA Playground access if you're learning independently.

5.Hands-On Example: An xrun Regression

Xcelium's single-command xrun driver is one of its most distinctive workflow features compared to the multi-step vlog/vopt/vsim pattern:

# Compile, elaborate, and simulate in one command
xrun -sv -uvm \
     -f filelist.f \
     -access +rwc \
     +UVM_TESTNAME=axi_write_read_test \
     -svseed 42 \
     -l run.log

# Incremental recompile on subsequent runs (skips unchanged sources)
xrun -sv -uvm -f filelist.f -incr +UVM_TESTNAME=axi_reset_test

# Multi-core build for a large regression
xrun -sv -uvm -f filelist.f -mce -j 8 +UVM_TESTNAME=full_soc_smoke

The -access +rwc switch is Xcelium's equivalent of Questa's +acc — it grants read/write/connect visibility into signals for waveform dumping and interactive debug, at the cost of some simulation performance, so production regression scripts typically drop it and only add it back when re-running a specific failing seed.

Tip Use -incr for iterative local development where you're only touching a handful of files. Reserve full recompiles for CI/nightly regression triggers so you're not silently simulating against stale object code.

Recap

  • Xcelium is Cadence's multi-core parallel simulator, extended through domain-specific Xcelium Apps.
  • SimAI adds ML-driven regression targeting and \u201ccousin bug\u201d discovery on top of existing regression data.
  • The core workflow is a single xrun command, versus Questa's separate vlog/vopt/vsim steps.
  • No free general-use edition exists; access is via a purchased license, university program, or EDA Playground.
Next Up · Part 4

JasperGold — Cadence's formal verification platform, and how proving properties differs from simulating them.

EDA Tools & Industry Guidance · Series
← Questa One Sim JasperGold →
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