Skip to main content

Virtual Memory: A Complete Guide to Paging, Page Tables, TLB, and Page Faults

Image
By

 


Virtual Memory: A Complete Guide to Paging, Page Tables, TLB, and Page Faults

Modern computers can run dozens of applications simultaneously, even when the available RAM is limited. This is possible because of Virtual Memory, one of the most important concepts in Computer Architecture and Operating Systems.

Virtual memory provides every process with the illusion of having a large, continuous memory space, even though the physical RAM is limited. It allows programs larger than the available RAM to execute efficiently while ensuring security, isolation, and better memory management.

What is Virtual Memory?

Virtual Memory is a memory management technique that allows the operating system to use secondary storage (SSD/HDD) along with RAM, making it appear as if the computer has more memory than physically installed.

Instead of directly accessing physical memory, every program works with virtual addresses. These virtual addresses are translated into physical addresses by the Memory Management Unit (MMU) using data structures maintained by the operating system.

Definition:
Virtual Memory is a technique that maps virtual addresses generated by the CPU to physical addresses in RAM, allowing efficient memory utilization and process isolation.

Why Do We Need Virtual Memory?

Without virtual memory, the operating system would face several limitations.

1. Programs can be larger than RAM

Suppose a system has 8 GB RAM, but a program requires 12 GB.

Without virtual memory:

  • Program cannot execute.

With virtual memory:

  • Frequently used data remains in RAM.
  • Less frequently used data is temporarily stored on disk.
  • Program executes normally.

2. Supports Multiprogramming

Modern operating systems run multiple applications simultaneously.

Example:

  • Chrome
  • VS Code
  • Spotify
  • Photoshop
  • Terminal

Each process receives its own virtual address space, preventing interference between programs.

3. Process Isolation and Protection

Every process has its own independent virtual memory.



Although both processes use identical virtual addresses, they map to completely different physical memory locations.

This provides:

  • Security
  • Isolation
  • Stability

A faulty program cannot overwrite another program's memory.

4. Better Memory Utilization

Only actively used pages remain in RAM.

Unused pages can be moved to disk.

This allows:

  • Higher RAM efficiency
  • More applications running simultaneously
  • Reduced memory wastage

Basic Idea of Virtual Memory

The CPU never directly accesses RAM.



Virtual Address vs Physical Address



Example



Paging

Virtual memory is implemented using Paging.

Instead of storing memory as one large block, both virtual memory and physical memory are divided into fixed-size blocks.



Each virtual page can be placed in any available physical frame.

Unlike segmentation, pages do not need to be contiguous.

Page and Page Frame

A Page is a fixed-size block in virtual memory.

A Page Frame is a fixed-size block in physical RAM.

Virtual Memory

Page 0
Page 1
Page 2

↓

Physical Memory

Frame 5
Frame 2
Frame 8

Notice that pages are stored in different physical locations.

Address Format

A virtual address is divided into two parts.




Page Table

A Page Table stores the mapping between virtual pages and physical frames.



Memory Translation Using Page Table



Every memory access requires:

  1. Read page table
  2. Read actual data

This results in two memory accesses, increasing latency.

Translation Lookaside Buffer (TLB)

A Translation Lookaside Buffer (TLB) is a small, fast associative cache inside the MMU.

It stores recently used page table entries to speed up address translation.

Instead of accessing the page table every time, the MMU first searches the TLB.

TLB Entry

A TLB entry typically contains:

Valid Bit
VPN (Virtual Page Number)
PFN (Physical Frame Number)
Permission Bits
Dirty Bit
Reference Bit

Address Translation Using TLB




Why TLB Improves Performance



Page Fault

A Page Fault occurs when the requested page is not currently present in physical RAM.

Instead, it resides on secondary storage (disk).

Page Fault Handling



What Happens During a Page Fault?

  1. CPU accesses a missing page.
  2. Hardware detects the fault.
  3. Control transfers to the operating system.
  4. OS finds the page on disk.
  5. A free frame is allocated (or an existing page is replaced using algorithms like FIFO or LRU).
  6. The page is copied from disk into RAM.
  7. The page table is updated.
  8. The TLB is updated.
  9. The interrupted instruction is restarted.

Example of Address Translation



Advantages of Virtual Memory

  • Allows execution of programs larger than physical RAM.
  • Supports efficient multitasking.
  • Improves overall memory utilization.
  • Provides process isolation and protection.
  • Simplifies programming using a contiguous virtual address space.
  • Enables demand paging, shared memory, memory-mapped files, and copy-on-write.
  • Reduces fragmentation through fixed-size pages.

Limitations of Virtual Memory

  • Address translation introduces overhead.
  • Page faults are expensive because disk access is much slower than RAM.
  • Large page tables consume memory.
  • Excessive page faults can cause thrashing, where the system spends more time swapping pages than executing programs.

Paging vs TLB







Key Points to Remember

  • Virtual memory gives each process the illusion of a large, contiguous address space.
  • The CPU generates virtual addresses, not physical addresses.
  • The MMU translates virtual addresses into physical addresses.
  • Memory is divided into fixed-size pages, while RAM is divided into frames.
  • A Page Table stores the mapping between pages and frames.
  • A TLB caches recently used page table entries to reduce translation time.
  • A TLB Hit enables fast address translation, while a TLB Miss requires consulting the page table.
  • A Page Fault occurs when a required page is absent from RAM, prompting the operating system to load it from disk.
  • Virtual memory improves memory utilization, security, multitasking, and overall system performance.

Conclusion

Virtual memory is a foundational concept in modern computer systems that enables efficient execution of applications regardless of physical RAM limitations. By combining paging, page tables, TLBs, and page fault handling, the operating system ensures that processes have isolated, secure, and efficient access to memory. Understanding these mechanisms is essential for students of Computer Architecture, Operating Systems, and system software, as they form the basis of efficient memory management in modern computing.

Labels:

Comments

Post a Comment

Popular posts from this blog

Module 1 — SystemVerilog Basics

By
VLSI Verification  •  SystemVerilog Series Module 1 — SystemVerilog Basics A complete, example-driven walkthrough of SystemVerilog fundamentals: data types, variables vs nets, arrays of every flavor, strings, enums, structs, unions, and typedef — the building blocks every verification engineer needs before UVM. 🧩 Beginner → Intermediate ⏱ ~25 min read 💻 Code Examples Included 📑 Table of Contents Introduction to SystemVerilog Verilog vs SystemVerilog Data Types: 2-State vs 4-State Logic Variables and Nets Arrays: Packed vs Unpacked Dynamic Arrays Queues Associative Arrays Strings Enumerations Structures Unions Typedef 1 Introduction to SystemVerilog SystemVerilog (IEEE 1800) is a unified hardware description and verification language (HDVL). It extends Verilog (IEEE 1364) with powerful constructs for design (interfaces, always_comb/always_ff, enhanced d...
Post a Comment
Read more

GPU Memory System & Interconnect: How Data Travels Inside a Modern GPU

By
GPU Memory System & Interconnect: How Data Travels Inside a Modern GPU Modern GPUs deliver incredible computing power by processing thousands of operations simultaneously. While compute cores often receive the spotlight, the real performance of a GPU depends heavily on how efficiently data moves between memory and compute units. A GPU memory system is designed to provide extremely high bandwidth while keeping latency as low as possible. This is achieved through a collection of specialized hardware components working together, including the Memory Controller, HBM/GDDR memory, Crossbar, Network-on-Chip (NoC), DMA Engine, PCIe Interface, and NVLink. In this article, we'll explore each component in detail and understand how they collectively enable high-performance parallel computing. Why Does GPU Memory Matter? Every GPU application—from gaming and graphics rendering to AI model training and scientific simulations—requires continuous movement of enormous amounts of data. For examp...
Post a Comment
Read more

Clock Domain Crossing (CDC): A Complete Beginner's Guide to Metastability, Synchronizers & Safe Data Transfer

By
Clock Domain Crossing (CDC): A Complete Beginner's Guide to Metastability, Synchronizers & Safe Data Transfer Modern System-on-Chip (SoC) designs rarely operate with a single clock. Instead, different modules such as CPUs, GPUs, memory controllers, communication interfaces, and peripherals often run at different clock frequencies or even use completely independent clock sources . When data moves from one clock domain to another, timing uncertainty can cause serious problems such as metastability , data corruption , and unpredictable system behaviour . This challenge is known as Clock Domain Crossing (CDC) . CDC is one of the most important topics in ASIC Design , RTL Design , ASIC Verification , FPGA Design , and SoC Architecture . Every modern chip—from smartphones to automotive processors—uses CDC techniques to ensure reliable communication between multiple clock domains. In this article, we'll explore CDC fundamentals, metastability, synchronization techniques, asynchro...
Post a Comment
Read more

AXI Verification Interview Questions and Real-World Debugging

By
AMBA Protocol Series · Part 10 of 10 AXI Verification Interview Questions and Real-World Debugging Common protocol violations, how to read them off a waveform, and a curated set of interview questions with concise, correct answers — the capstone of the core 10-day series. AMBA Protocol Series: From APB & AHB to AXI — A Complete Guide for VLSI Engineers This wraps up the core 10-day series. Everything here draws directly on Days 1–9 — if any answer below feels unfamiliar, that's a good signal for which earlier post to revisit. (If you want to go further, see the 20-day extended list at the end of this post.) In This Article Common Protocol Violations Debugging From a Waveform Interview Questions and Answers Series Recap Extending the Series 1. Common Protocol Violations VALID deasserted before handshake — a source drops VALID before READY ever went high (violates the Day 8 stabi...
Post a Comment
Read more

Cache Basics and Cache Mapping Techniques

By
  Cache Basics and Cache Mapping Techniques  Modern processors execute billions of instructions every second. However, processor speed has increased much faster than main memory (RAM) speed. This difference, known as the memory wall , creates a performance bottleneck because the CPU often has to wait for data from slower memory. To solve this problem, computer systems use cache memory —a small, high-speed memory located between the CPU and the main memory. In this article, we will understand the fundamentals of cache memory, the principle of locality, cache organization, and the three major cache mapping techniques. What is Cache Memory? Cache memory is a small, high-speed memory that stores copies of frequently accessed data from the main memory. Since accessing cache is much faster than accessing RAM, the CPU first checks whether the required data is available in the cache. If the data is found in the cache, it is called a cache hit . Otherwise, the CPU fetches the dat...
Post a Comment
Read more

Timing Basics in Static Timing Analysis (STA): Delay Models, Sequential Timing, and Wire Delays

By
Timing Basics in Static Timing Analysis (STA) Static Timing Analysis (STA) is one of the most important verification techniques used in modern VLSI design. Before a chip is manufactured, engineers must verify that every signal reaches its destination within the required clock period. Even if a design passes functional simulation, it may still fail after fabrication because of timing violations. Unlike simulation, Static Timing Analysis mathematically analyzes every timing path without applying input test vectors. This makes STA significantly faster and capable of analyzing millions of timing paths efficiently. Table of Contents What is Static Timing Analysis? Why STA is Required Propagation Delay Contamination Delay Cell Delay Models Combinational Gate Delay Sequential Timing Setup Time Hold Time Wire Delay RC Delay Model PVT Corners Worked Examples Interview Questions Key Takeaways What is Static Timing Analysis? Static Ti...
Post a Comment
Read more

Computer Architecture Interview Question Part 1

By
Skip to content Computer Architecture Interview Series Part 1 · CPU Basics · RISC vs CISC · ISA 50 Most Asked Computer Architecture Interview Questions (Part 1) The foundational round every VLSI, ASIC, and CPU design interview opens with: instruction set architecture, RISC vs CISC trade-offs, Von Neumann vs Harvard design, registers, endianness, and the fetch-decode-execute cycle — explained the way interviewers actually expect you to answer.  40 Questions (Q1–Q40) ⌛ 22 min read  VLSI & Computer Architecture Interviews On this page Foundations of Computer Architecture RISC vs CISC — Core Differences Von Neumann, Harvard & the Semantic Gap Architecture Styles, Endianness & Registers ILP, VLIW, Superscalar & Amdahl's Law Register Files, Microcontrollers & the Fetch Cycle Tip...
Post a Comment
Read more