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AXI Burst Transactions Explained: LEN, SIZE, BURST and Address Calculation

AMBA Protocol Series · Part 7 of 10

AXI Burst Transactions Explained: LEN, SIZE, BURST and Address Calculation



INCR, WRAP, and FIXED burst types, exactly how burst length and beat size are encoded, and the address-generation math for every beat in a burst.

AMBA Protocol Series: From APB & AHB to AXI — A Complete Guide for VLSI Engineers

Burst handling is one of the most reliable ways interviewers separate candidates who've memorized AXI signal names from candidates who actually understand the protocol. This post gives you the exact math, not just the concepts.

1.AxLEN: Burst Length

AWLEN / ARLEN encodes the number of data beats minus one. So AxLEN = 0 means a 1-beat burst, and AxLEN = 15 means a 16-beat burst. AXI4 supports up to 256 beats for INCR bursts (AxLEN up to 255), but WRAP and FIXED bursts are limited to a maximum of 16 beats.

2.AxSIZE: Bytes per Beat

AxSIZEBytes per Beat
0b0001 byte
0b0012 bytes
0b0104 bytes
0b0118 bytes
0b10016 bytes
...up to 128 bytes (0b111)

AxSIZE can never exceed the data bus width — you cannot request a 16-byte beat on a 4-byte-wide data bus.

3.AxBURST: INCR, WRAP, FIXED

  • FIXED (0b00) — every beat uses the same address. Used for accessing a single hardware register or FIFO port repeatedly.
  • INCR (0b01) — address increments by the beat size after each beat. The general-purpose case for sequential memory access.
  • WRAP (0b10) — address increments like INCR, but wraps back to the start of an aligned address block once it hits the upper boundary. Used for cache-line fills, where you want to fetch the critical (requested) word first and wrap around to fill the rest of the line.

4.Address Calculation Walkthrough

INCR Burst — AWADDR=0x100, AWSIZE=4 bytes, AWLEN=3 (4 beats) // Beat address = start_address + (beat_index * bytes_per_beat) Beat 0: 0x100 Beat 1: 0x104 Beat 2: 0x108 Beat 3: 0x10C
⚠️ Common Mistake
Don't confuse AxSIZE (bytes per beat, fixed for the whole burst) with the total burst length in bytes. Total bytes transferred = (AxLEN + 1) × bytes-per-beat. In the example above: (3+1) × 4 = 16 bytes total.

5.WRAP Boundary Calculation

For a WRAP burst, the "wrap boundary" is the address aligned to the total burst size: wrap_boundary = (start_address / total_bytes) × total_bytes. The address increments as INCR normally would until it reaches wrap_boundary + total_bytes, at which point it wraps back to wrap_boundary and continues from there.

WRAP Burst — AWADDR=0x10C, AWSIZE=4 bytes, AWLEN=3 (4 beats, total=16 bytes) // wrap_boundary = (0x10C / 16) * 16 = 0x100 Beat 0: 0x10C (starting address, the "critical" word) Beat 1: 0x100 (wraps back to the boundary) Beat 2: 0x104 Beat 3: 0x108

6.Burst Constraints You Must Know

  • A burst must never cross a 4KB address boundary — this is an AXI4 rule that exists because most interconnects and memory controllers are organized around 4KB pages.
  • WRAP bursts require AxLEN + 1 to be 2, 4, 8, or 16 (a power of two) — any other length is not a legal WRAP burst.
  • The starting address for a WRAP burst must be aligned to the size of a single beat (AxSIZE), not the whole burst.

Recap: What We Covered Today

  • AxLEN encodes beats minus one; AxSIZE encodes bytes per beat; total bytes = (AxLEN+1) × bytes-per-beat.
  • INCR increments address every beat; FIXED repeats the same address; WRAP increments but wraps at an aligned boundary.
  • Bursts can never cross a 4KB boundary, and WRAP burst lengths must be a power of two.
Coming Up — Day 8

AMBA Protocol Handshake: VALID and READY Explained

Tomorrow we go deep on the handshake rules that govern every AMBA channel — including the specific timing rules and backpressure mistakes that show up constantly in RTL bugs and verification checks.

◀ Day 6: AXI Variants Day 7 of 10 Day 8: VALID/READY Handshake ▶

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