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70 Analog IC Design Interview Questions Every VLSI/Analog Aspirant Should Practice
A structured Q&A walkthrough — from MOSFET basics to PLL loop filters — with concise, interview-ready answers.
If you are preparing for an analog or mixed-signal interview, you have probably noticed that the same families of questions keep repeating across companies — small-signal models, mirrors, differential pairs, frequency response, data converters, PLLs. The questions are not random; they test whether you can reason from device physics upward to circuit behaviour.
This post walks through 70 of the most-asked analog IC design interview questions, grouped by topic, with answers written the way you would want to answer them on a whiteboard — short, correct, and physical rather than algebraic.
Try to answer each question in your own words first, then read the answer. The goal is understanding, not memorising. Revisit weekly with a timer — 2 minutes per question is a realistic interview budget.
01Basic Concepts
Device-level questions. Expect the interviewer to probe why, not just what.
Q1.Explain MOSFET structure and operation. Device
A MOSFET is a four-terminal device — Gate, Source, Drain, Body — built on a lightly doped silicon substrate. The gate is a conductor separated from the channel region by a thin oxide (SiO₂ or high-κ), while source and drain are heavily doped regions of opposite type to the body. Applying a gate-to-source voltage above threshold inverts the surface under the oxide, forming a conducting channel between source and drain whose charge density is controlled capacitively by the gate.
Q2.What are the regions of operation of a MOSFET? Device
Three main regions: cut-off (VGS < VTH, no channel, ideally no current), triode / linear (VGS > VTH and VDS < VGS−VTH, the channel is continuous and the device behaves like a voltage-controlled resistor), and saturation (VDS ≥ VGS−VTH, the channel pinches off at the drain and current becomes nearly independent of VDS). A fourth, subthreshold, operates below VTH with exponentially small current and is important for low-power design.
Q3.What is threshold voltage? Device
Threshold voltage VTH is the gate-to-source voltage at which the surface under the gate becomes strongly inverted — that is, the mobile carrier concentration at the surface equals the dopant concentration in the bulk. Below VTH the channel conducts only weakly (subthreshold), and above it the device turns on. VTH depends on gate material work-function, oxide thickness, substrate doping and body bias (body effect).
Q4.Draw and explain the I–V characteristics. Device
In triode, ID rises almost linearly with VDS and curves over as VDS approaches VGS−VTH. In saturation, ID flattens into a nearly horizontal line (ID = ½·Î¼Cox·(W/L)·(VGS−VTH)²·(1+λVDS)), with a small positive slope due to channel-length modulation. Each VGS traces its own curve; higher VGS means higher saturation current.
Q5.What is the small-signal model of a MOSFET? Small signal
The small-signal model replaces the nonlinear device around an operating point with a linear equivalent: a transconductance current source gm·vgs between drain and source, a drain-source output resistance ro, and parasitic capacitances Cgs, Cgd, Cdb, Csb. A body-transconductance gmb·vbs is added when the source and body are at different potentials.
Q6.Define output resistance ro. Small signal
ro is the small-signal resistance looking into the drain in saturation, defined as ro = ∂VDS/∂ID ≈ 1/(λID). It arises from channel-length modulation — as VDS rises, the pinch-off point moves toward the source, shortening the effective channel and increasing ID slightly. A higher ro means a more ideal current source and higher intrinsic gain.
Q7.What is the body effect? Device
Body effect is the increase in threshold voltage when the source-to-body voltage VSB becomes non-zero. A reverse-biased body-source junction widens the depletion region under the channel, requiring more gate charge to invert the surface. It is modelled as VTH = VTH0 + γ(√(2φF+VSB) − √(2φF)) and is important in stacked devices like cascodes and source followers.
Q8.Explain channel-length modulation. Device
In saturation, increasing VDS pushes the pinch-off point from the drain edge toward the source. The effective channel length Leff shrinks, so ID rises slightly with VDS instead of being perfectly flat. This is captured by the parameter λ (≈ 1/VA), giving a finite ro and limiting intrinsic gain.
Q9.What is the significance of gm, ro and gm·ro? Small signal
gm measures how strongly VGS controls ID; ro measures how weakly VDS affects ID. Their product gm·ro is the intrinsic voltage gain of a MOSFET — the maximum gain achievable with an ideal current-source load. In modern short-channel CMOS it is typically 20–40, which is why cascoding and multi-stage topologies are used to reach higher gain.
If asked how to increase gm·ro: increase L (raises ro faster than it drops gm), reduce VOV, or cascode.
Q10.What are PVT variations and why do they matter? Basics
PVT = Process, Voltage, Temperature. Process variation covers fab-to-fab and die-to-die spread in VTH, μ, oxide thickness, etc.; voltage variation covers supply drift and droop; temperature variation covers device-level mobility and VTH drift from, say, −40 °C to 125 °C. Analog circuits must meet specs across all PVT corners simultaneously, which is why reference generators, bias networks, and compensation schemes are designed with PVT robustness as a first-class goal.
02Amplifier Circuits
The three fundamental topologies and what you build out of them.
Q11.Explain the common-source amplifier. CS
Input at the gate, output at the drain, source grounded (or at a fixed potential). It gives high voltage gain Av ≈ −gm·(ro ∥ RL), high input impedance, moderate output impedance, and inverting output. It is the workhorse gain stage in CMOS analog design.
Q12.Explain the common-drain (source-follower) amplifier. CD
Input at the gate, output at the source, drain tied to supply. Voltage gain is slightly less than 1 (Av = gmR/(1+gmR+gmbR)), input impedance is high, and output impedance is low (≈ 1/gm). Used as a buffer or level shifter and to drive low-impedance loads.
Q13.Explain the common-gate amplifier. CG
Input at the source, output at the drain, gate at a fixed bias. Gain is Av ≈ gm·(ro ∥ RL) and non-inverting. It has low input impedance (≈ 1/gm) and high output impedance, which makes it excellent as a current buffer and as the top device of a cascode.
Q14.How do you compute gain and output resistance of an amplifier? Analysis
Replace the MOSFETs with their small-signal models, short all independent sources, and solve by inspection. Output resistance is found by applying a test voltage vx at the output with the input shorted and computing Rout = vx/ix. Gain is then −Gm·Rout, where Gm is the short-circuit transconductance from input to output.
Q15.Explain the cascode amplifier. Cascode
A common-source stage with a common-gate stage stacked on top. The CG transistor keeps VDS of the input device nearly constant, which boosts output resistance to roughly gm2·ro2·ro1 and therefore gain. It also reduces the Miller effect, improving bandwidth, at the cost of reduced output swing.
Q16.What is a current mirror? Current mirror
A current mirror copies a reference current IREF to one or more output branches. Simplest form: diode-connect M1, tie its gate to M2's gate, size both equally — then IOUT = IREF·(W/L)2/(W/L)1. Non-idealities are mismatch, finite output resistance, and VDS dependence, which cascode mirrors improve.
Q17.Explain the differential pair. Differential
Two matched transistors sharing a common tail current source steer that current between two output branches based on the differential input (Vin+ − Vin−). It rejects common-mode signals, has differential transconductance gm per side, and is the input stage of almost every op-amp, comparator, and LNA.
Q18.What is an active load? Active load
A transistor (typically a current mirror) used as the load of an amplifier instead of a passive resistor. It gives a much higher small-signal impedance (ro) in the same area, which raises gain dramatically, while sinking the DC bias current cleanly. Trade-off: more noise and more mismatch than a resistor.
Q19.What is an operational amplifier? Op-amp
An op-amp is a high-gain, differential-input, single-ended-output amplifier intended for use in feedback. Ideal op-amp assumptions: infinite open-loop gain, infinite input impedance, zero output impedance, infinite bandwidth, zero offset. Real op-amps approach these over a limited range of signal and frequency, and the designer's job is to make the non-idealities small enough for the application.
Q20.Why do we need multi-stage amplifiers? Multi-stage
A single CMOS stage rarely gives enough DC gain (typically 20–40 dB with cascoding at modern nodes) and enough output swing and a low enough output impedance to drive the next stage. Multi-stage amplifiers decouple these roles: an input stage for gain and CMRR, intermediate stages for added gain, and an output stage for drive. The price is that each extra pole must be managed for stability (hence Miller compensation).
Q21.Explain the frequency response of an amplifier. Frequency
Capacitances in the device and at the nodes form poles and zeros that cause the gain to roll off with frequency. A typical single-pole amplifier is flat up to its dominant pole, then rolls off at −20 dB/dec until it crosses unity gain. Multi-pole amplifiers may show additional roll-off and phase shift, which govern stability in feedback.
Q22.What is the Miller effect and how do we compensate for it? Stability
A capacitor Cf between the input and output of an inverting gain stage of gain −A appears at the input node as Cf·(1+A) — the Miller multiplication. In an op-amp this is turned to advantage: adding Cc across the second stage splits the two poles apart (dominant pole moves down, non-dominant pole moves up — "pole splitting"), creating a well-behaved single-pole roll-off. A nulling resistor Rz in series with Cc removes the RHP zero that otherwise degrades phase margin.
03Biasing & References
How you set and hold operating points across process and temperature.
Q23.What types of current mirrors exist? Current mirror
Common variants: simple (two devices, poor Rout), cascode (two stacked pairs, high Rout, large Vmin), wide-swing cascode (same high Rout with much lower minimum output voltage), Wilson (feedback-based, good matching), and low-voltage variants that use biasing tricks to keep all devices in saturation at reduced headroom.
Q24.Explain the Wilson current mirror. Current mirror
The Wilson mirror adds a third transistor in feedback with the mirror output, forcing IOUT to track IREF very accurately and raising the output resistance to about (gm·ro·ro)/2. It is popular where accuracy matters more than headroom; the "improved" (four-transistor) Wilson balances the VDS of the input pair for even better matching.
Q25.What is a cascode current mirror and why use it? Current mirror
A cascode mirror stacks a second common-gate device on top of each mirror transistor, shielding the mirror from VDS variations at the output node. Output resistance becomes roughly gm,cas·ro,cas·ro,mir — orders of magnitude higher than a simple mirror — making the copied current far more VDS-independent at the cost of two VDSsat of headroom.
Q26.What are the common biasing techniques? Biasing
Resistor-based (VGS set by a resistor divider — simple but PVT-sensitive), current-mirror biasing (reference distributed by mirrors), constant-gm biasing (self-biased loop that pins gm against a resistor), and bandgap-based (voltage/current derived from a bandgap for excellent PVT stability). Choice is driven by accuracy, power, and area.
Q27.Explain the bandgap reference. Bandgap
A bandgap reference sums a CTAT voltage (VBE, negative tempco ≈ −2 mV/°C) with a PTAT voltage (ΔVBE amplified by a factor K) so that the two tempcos cancel. The result is a voltage near the silicon bandgap (≈ 1.2 V) that is nearly flat with temperature and highly supply-independent — the reference backbone for ADCs, DACs, LDOs, and PLLs.
Q28.What are PTAT and CTAT currents/voltages? Bandgap
PTAT (Proportional To Absolute Temperature) rises linearly with T — e.g., the difference ΔVBE between two BJTs with different current densities. CTAT (Complementary To Absolute Temperature) falls with T — e.g., VBE of a forward-biased junction. Weighted sums of PTAT and CTAT are the building blocks of temperature-stable (bandgap) and intentionally temperature-sensitive (temperature sensor) circuits.
Q29.Why do bandgap references need start-up circuits? Bandgap
Bandgap and constant-gm loops have two stable states: the intended operating point and a degenerate zero-current state. A start-up circuit injects a small kick during power-up (often a weak device that pulls one node when the loop is dead) to push the circuit out of the zero state. Once the loop is alive, the start-up stage switches off so it does not disturb the reference.
Q30.How do process and temperature affect analog circuits? Reference
Process spreads VTH, μ, oxide thickness, and resistor/capacitor sheet values; temperature changes μ (lowers with T) and VTH (lowers with T) and shifts VBE. The combined effect moves bias currents, gain, offset, and bandwidth. Analog designers combat this with ratio-based design (match-dependent, not absolute-value-dependent), self-biased loops, and references anchored to physical constants (silicon bandgap).
If an interviewer asks you to "design a current source," answer in two layers: (1) a reference that is PVT-stable (bandgap-derived or constant-gm), and (2) a cascode mirror that distributes it with high output impedance. Mentioning both signals you think like an IC designer.
04Analog Building Blocks
Comparators, references, switches — the "verbs" of analog design.
Q31.How is a comparator designed? Comparator
A comparator is an op-amp optimised for speed and open-loop operation. A common structure is a differential pre-amp followed by a positive-feedback regenerative latch: the pre-amp amplifies the small input difference, then the latch — triggered by a clock — snaps the output to the nearest rail. There is no feedback compensation, so slewing and metastability (not phase margin) are the main design concerns.
Q32.What is hysteresis in a comparator? Comparator
Hysteresis creates two different switching thresholds — one for a rising input and a lower one for a falling input. The resulting dead-band prevents the output from chattering when a noisy input hovers around a single threshold. It is implemented with positive feedback (resistor divider in BJT, or cross-coupled transistors in CMOS).
Q33.What is a Schmitt trigger? Comparator
A Schmitt trigger is a comparator with built-in hysteresis — distinct upper (VH) and lower (VL) thresholds. It is used to clean up slow or noisy transitions into sharp digital edges (e.g., at a chip input pad) and as a basic building block for relaxation oscillators and debouncers.
Q34.What is a voltage reference and how is it designed? Reference
A voltage reference generates a precise, PVT-stable DC voltage. The dominant architecture is the bandgap (see Q27). Alternatives include Zener-based references (used in some high-voltage analog) and buried-contact or floating-gate references. Key specs are initial accuracy, temperature coefficient (ppm/°C), PSRR, noise, and long-term drift.
Q35.How do you design a current source/sink? Current source
Start from a PVT-stable reference current (bandgap or constant-gm), then distribute via cascode current mirrors for high output impedance. Set VOV based on headroom (small VOV for low voltage, larger for less mismatch), choose L for better ro and matching, and lay out as a common-centroid array of matched fingers.
Q36.What is a level shifter? Level shifter
A level shifter translates a signal between two different voltage domains — for example, from a 0.9 V digital core to a 1.8 V I/O rail, or across the inputs of a rail-to-rail op-amp. CMOS implementations use cross-coupled PMOS pulls-up with NMOS pull-down drivers (DCVSL) to translate signal levels while blocking leakage.
Q37.How do you design an analog switch? Switch
A single NMOS switch has low on-resistance only for low Vin; a single PMOS, only for high Vin. For a rail-to-rail switch, use a complementary pair (transmission gate). Watch for charge injection (clock feedthrough injects charge via Cgs/Cgd) and signal-dependent Ron; dummy switches and bootstrapping reduce these.
Q38.What is a transmission gate? Switch
A transmission gate is a parallel NMOS–PMOS pair driven by complementary clocks. The NMOS passes a strong 0 and a weak 1; the PMOS passes a strong 1 and a weak 0. Together they conduct over the full supply range with low, more symmetric Ron, making them the standard switch for sample-and-hold and switched-capacitor circuits.
05Frequency Response
Poles, zeros, bandwidth, stability — the small-signal AC view.
Q39.What are poles and zeros? Frequency
In the transfer function H(s) = N(s)/D(s), poles are roots of D(s) — frequencies at which the magnitude response falls off by 20 dB/dec and the phase lags an additional 90°. Zeros are roots of N(s) — they add 20 dB/dec of rise and either +90° (LHP zero) or −90° (RHP zero) of phase. Pole/zero locations determine bandwidth, step response, and stability.
Q40.What is -3 dB bandwidth? Frequency
The −3 dB bandwidth is the frequency at which the voltage gain magnitude drops to 1/√2 (≈ 0.707) of its mid-band value — equivalently, where output power halves. For a single-pole system it equals the pole frequency; for cascaded single-pole stages with equal pole frequencies, overall −3 dB shrinks by a factor √(21/n−1).
Q41.What is the gain-bandwidth product? Frequency
For a single-pole amplifier, GBW = A0·fp = fu, i.e. DC gain times dominant-pole frequency equals the unity-gain frequency. It is a conserved quantity: trading DC gain for bandwidth via feedback preserves GBW. It is the figure of merit for a given bias current — pushing GBW higher usually means burning more current to raise gm.
Q42.What is phase margin? Stability
Phase margin (PM) is the extra phase above −180° that the loop gain has at the frequency where |T(jω)| = 1 (the unity loop-gain crossover). PM > 0 means stable; 45°–60° is a typical design target balancing stability, ringing, and settling. Lower PM gives more peaking and ringing; too much slows the step response.
Q43.How do you analyse a Bode plot? Analysis
Plot magnitude in dB and phase in degrees on a log-frequency axis. Each LHP pole adds −20 dB/dec of slope at its corner and ultimately −90° of phase; each LHP zero adds +20 dB/dec and +90°. The DC gain is the flat value before the first pole; the unity-gain crossover and the phase at that frequency give you GBW and phase margin at a glance.
Q44.What is slew rate? Dynamic
Slew rate (SR) is the maximum dVout/dt the amplifier can deliver — a large-signal limit set by how fast the available tail current can charge the compensation capacitor: SR ≈ Itail/Cc. Small-signal GBW governs linear response; slew rate dominates on large steps. Both must be designed for the application's step size.
Q45.What is the unity-gain frequency? Frequency
The unity-gain frequency fu (also called fT for a device or GBW for a single-pole op-amp) is the frequency at which |gain| = 1 (0 dB). For a well-compensated op-amp it is approximately gm1/(2Ï€·Cc), setting the fundamental speed of the amplifier in feedback.
Q46.What are the stability criteria for a feedback amplifier? Stability
From the Bode criterion: a negative-feedback loop is stable if the phase of the loop gain is more positive than −180° at the frequency where |T(jω)| = 1. From the Nyquist criterion: the Nyquist plot of the loop gain must not encircle the −1 point. In practice: ensure one dominant pole well below the next pole, aim for ~60° PM and > 10 dB gain margin, and verify across PVT corners.
06Data Converters & PLL
Where analog meets digital — and where interviewers spend the most time.
Q47.What ADC architectures should I know? ADC
Common ADC families: Flash (very fast, low resolution, 2N−1 comparators), SAR (medium speed, 8–16 bits, energy-efficient), Pipeline (high speed and resolution, used in video and comms), Delta-Sigma (very high resolution at low-to-moderate speed via oversampling and noise shaping), and Integrating / dual-slope (DVMs, very linear, slow). Each trades speed, resolution, and power differently.
Q48.What DAC architectures should I know? DAC
Main DAC families: Binary-weighted (compact but mismatch grows with resolution), R-2R ladder (uses only two resistor values, better matching), Thermometer-coded (monotonic by construction, used for high accuracy), Segmented (hybrid of thermometer-MSB and binary-LSB for area/accuracy balance), and Delta-Sigma DACs (oversampled, noise-shaped, typical in audio).
Q49.Define SNR, ENOB and resolution. ADC/DAC
Resolution is the number of bits N; LSB = VFS/2N. SNR is the ratio of signal power to noise power; for an ideal N-bit ADC with a full-scale sine, SNR = 6.02N + 1.76 dB. ENOB back-solves that formula from measured SINAD: ENOB = (SINAD − 1.76)/6.02. ENOB is the honest number you should quote.
Q50.Explain sampling and aliasing. ADC
Sampling at fs captures the input at discrete instants. By the Nyquist theorem, a signal can be reconstructed only if fs > 2·fmax. Content above fs/2 folds back into baseband as aliases that are indistinguishable from real signals. An anti-alias filter before the sampler is mandatory for any practical ADC.
Q51.What is a sample-and-hold circuit? S/H
A sample-and-hold freezes the analog input on a capacitor during the ADC's conversion. During "sample" a switch closes and Chold tracks Vin; during "hold" the switch opens and Chold keeps the voltage for the comparator(s). Key non-idealities: aperture jitter, droop (leakage), charge injection, and signal-dependent Ron — all of which bootstrapped switches help mitigate.
Q52.Explain a Flash ADC. ADC
A Flash ADC uses a resistor-string divider to generate 2N−1 reference voltages and compares the input against all of them in parallel with 2N−1 comparators. Thermometer-code output is encoded to binary. It is the fastest architecture (single-clock conversion) but hardware and power scale exponentially with N, so it is limited to ≤ 6–8 bits in practice.
Q53.Explain a SAR ADC. ADC
A SAR ADC performs a binary search: on each clock cycle, a DAC output is set to the current best guess, a comparator decides whether the input is above or below it, and the SAR logic refines the next bit. Conversion takes N cycles for N bits. It is extremely energy-efficient and dominates the 8–16-bit, kHz-to-100 MHz space.
Q54.Explain a Delta-Sigma ADC. ADC
A Delta-Sigma ADC oversamples by a factor OSR and uses a feedback loop (a Σ integrator followed by a coarse quantiser whose output is fed back through a DAC) to shape the quantisation noise toward high frequencies. A digital low-pass filter / decimator then removes the shaped noise, leaving very high effective resolution in the signal band. Used in audio, instrumentation, and precision sensors.
Q55.Explain the PLL basics. PLL
A PLL is a feedback loop that locks the phase (and therefore frequency) of a VCO to a reference. Its building blocks are a phase/frequency detector, a charge pump, a loop filter, a VCO, and an optional divider in the feedback path (for frequency multiplication). Design handles are loop bandwidth, phase margin, reference spur, and jitter.
Q56.What is a phase detector? PLL
A phase detector produces an output proportional to the phase difference between two inputs. XOR and multiplier types work for sinusoids; the dominant block in modern PLLs is the Phase-Frequency Detector (PFD) — two flip-flops with reset — which outputs UP/DOWN pulses and provides both phase and frequency information, giving reliable lock-in from any initial condition.
Q57.What is a charge pump? PLL
A charge pump converts PFD UP/DOWN pulses into current into or out of the loop filter. During UP it sources ICP; during DOWN it sinks ICP; when both or neither are asserted, it is high-impedance. Mismatch between source and sink currents causes reference spurs and static phase offset, so matching and current-steering techniques are key.
Q58.How is a PLL loop filter designed? PLL
For a charge-pump PLL, a 2nd-order passive loop filter — a series R-C from the charge-pump node to ground, with a shunt C2 for ripple suppression — is standard. R and C set the loop zero (which gives phase margin); the ratio C/C2 is typically 10–20. Loop bandwidth is chosen as roughly 1/10 of the reference frequency and traded off against jitter and reference spurs.
07Miscellaneous & Application
Regulators, noise, layout — the questions that separate textbook knowledge from tape-out-ready design.
Q59.What is an LDO regulator? LDO
A Low-Dropout linear regulator holds VOUT constant with a small headroom (VIN − VOUT) — often a few hundred millivolts. It uses an error amplifier that drives a pass device (usually a PMOS) in a negative-feedback loop that compares a scaled VOUT against a bandgap reference. Design concerns are stability (output capacitor and ESR), transient response, PSRR, and quiescent current.
Q60.What is PSRR (Power-Supply Rejection Ratio)? LDO
PSRR = 20·log(ΔVsupply/ΔVout), measuring how well a circuit rejects supply noise. In op-amps it is typically high at DC and rolls off with frequency as the error amp's gain falls. In LDOs it is a headline spec because any supply ripple that leaks through directly corrupts the regulated rail used by sensitive analog blocks.
Q61.What are line regulation and load regulation? LDO
Line regulation is ΔVOUT/ΔVIN at fixed load — how much the output moves when the input supply moves. Load regulation is ΔVOUT/ΔILOAD at fixed VIN — how much the output droops when load current changes. Both improve with higher loop gain, better pass-device ro, and good layout.
Q62.What are the main noise sources in a MOSFET circuit? Noise
Three dominant sources: thermal noise from the channel (white, PSD = 4kTγ/gm referred to the input), flicker (1/f) noise from oxide traps (dominant at low frequency, worse in PMOS devices in most processes — actually, usually worse in NMOS, but process-dependent), and shot noise in gate-leakage currents at very thin oxides. Resistors contribute additional thermal noise 4kTR.
Q63.What is device mismatch and why does it matter? Mismatch
Mismatch is the random variation between nominally identical devices due to random dopant fluctuation, line-edge roughness, and oxide thickness variation. For MOSFETs, σ(VTH) ∝ 1/√(W·L) (Pelgrom's law). Mismatch limits op-amp offset, mirror accuracy, ADC linearity, and comparator decision thresholds; it is combatted with larger devices, common-centroid layout, and chopping/auto-zero.
Q64.What are important analog layout considerations? Layout
Match-critical devices (differential pair, mirror arrays) laid out in common-centroid or interdigitated patterns with dummy fingers at the edges; same orientation; minimum spacing between matched gates. Routed signals use shielded or symmetric paths; sensitive analog nets kept away from aggressive digital. Separate analog and digital supplies and grounds, with guard rings around noisy or sensitive blocks.
Q65.What are the ESD basics for IC pads? Reliability
ESD events (HBM, MM, CDM models) can discharge several amps through a pin in nanoseconds. ESD protection clamps the pad voltage below the gate-oxide breakdown by routing current through dedicated structures (diodes to supply and ground, GGNMOS, SCR). Design must ensure the clamp triggers before the core transistors see damaging voltage, and that current paths are low-impedance all the way to the power rails.
Q66.What are the main low-power design techniques? Low power
Operate transistors in sub-threshold / weak inversion for maximum gm/ID; use clock gating and power gating to shut down unused blocks; DVFS to scale supply with workload; duty-cycling for intermittent loads; adiabatic / charge-recycling tricks for switched-capacitor circuits; and architecture choices (SAR vs flash) that minimise energy per conversion.
Q67.What is the difference between analog and digital design? Conceptual
Digital design treats signals as discrete logic levels and relies on margin and automated synthesis; the critical questions are timing, power, and area. Analog design treats signals as continuous and must manage noise, mismatch, nonlinearity, and PVT margin by hand — no synthesis step collapses the design space. Analog is less portable across process nodes and relies heavily on topology and layout craft.
Q68.What are the main analog design trade-offs? Conceptual
The classic trade pentagon: speed, gain, noise, power, and swing (headroom), with linearity and area in the background. For example: more gm buys speed and lowers noise but costs current; longer L buys gain and matching but costs bandwidth and area; cascoding buys gain and PSRR but costs headroom. Good analog design is choosing which to sacrifice for which.
If asked "what is the most important trade-off?", resist naming one — the correct answer is "it depends on the spec that is hardest to meet." That alone shows design maturity.
Q69.What is latch-up and how do you prevent it? Reliability
Latch-up is a destructive short between supply and ground through the parasitic PNPN (SCR) structure formed by adjacent PMOS and NMOS wells. Once triggered — usually by a transient that forward-biases a well-substrate junction — it latches on and can only be cleared by removing power. Prevention: guard rings around I/O and large switching blocks, close well/substrate taps, minimum spacing between n+ and p+ in different wells, and well-defined pickup resistance.
Q70.What is clock jitter and how does it affect sampled systems? Noise
Jitter is the random variation in a clock edge's position relative to its ideal time. In a sampled system, jitter σt translates input slew-rate noise directly into sampled voltage noise: for a full-scale sine at frequency fin, SNRjitter = −20·log(2Ï€·fin·Ïƒt). It is the hard ceiling on ADC performance at high input frequencies, so clean clock generation (low-jitter PLL, clean supply) is as critical as the ADC core itself.
Quick recap
- Device basics — know the three regions of operation, the small-signal model, and why gm·ro is the magic number.
- Topologies — be able to draw CS, CD, CG, cascode, and differential pair from memory and derive gain by inspection.
- References & biasing — bandgap, PTAT/CTAT, start-up, and cascode mirrors are the plumbing of every analog chip.
- Frequency response — poles, zeros, phase margin, slew rate, and GBW cover 90% of op-amp interview questions.
- Data converters & PLL — know which architecture fits which speed/resolution corner, and the role of each PLL block.
- Applied topics — LDO stability, PSRR, mismatch, layout, ESD, and latch-up are where real-world designs live or die.
Keep practising
Set a 2-minute timer per question and go through this list once a week until each answer feels like a reflex.
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